AD7293 datasheet(49/78 Pages) AD

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Data Sheet

AD7293

Rev. B | Page 49 of 78

LOW LIMIT 0 (PAGE 0x06)

Table 61. Low Limit 0 (Page 0x06)

Address

(Hex)

Name

Byte1

Access

Type1

Default

Value1

0x00

No op

N/A

0x00

0x01

Page select pointer

R/W

0x00

0x02

Conversion command2

N/A

0x03

Result

0x0000

0x04

DAC enable

R/W

0x00

0x05

GPIO

R/W

0x00

0x0C

Device ID

0x0018

0x0F

Software reset

R/W

0x0000

0x10

VIN0 low limit

R/W

0x0000

0x11

VIN1 low limit

R/W

0x0000

0x12

VIN2 low limit

R/W

0x0000

0x13

VIN3 low limit

R/W

0x0000

0x20

TSENSEINT low limit

R/W

0x0000

0x21

TSENSED0 low limit

R/W

0x0000

0x22

TSENSED1 low limit

R/W

0x0000

0x28

ISENSE0 low limit

R/W

0x0000

0x29

ISENSE1 low limit

R/W

0x0000

0x2A

ISENSE2 low limit

R/W

0x0000

0x2B

ISENSE3 low limit

R/W

0x0000

N/A means not applicable.

Not a physical register.

VINx Low Limit Registers (Register 0x10 to Register 0x13)

These read/write 16-bit registers set the low limits for the four

input channels.

Temperature Sensor (TSENSEx) Low Limit Registers

(Register 0x20 to Register 0x22)

These read/write 16-bit registers set the low limits for the three

temperature sensor channels.

Table 62. Temperature Sensor Low Limit Registers

(Register 0x20 to Register 0x22)

Bit Number(s)

Bit Name

Description

D15

B11

0: −256°C (default)

1: 0°C

D14

B10

0: 0°C (default)

1: 128°C

D13

0: 0°C (default)

1: 64°C

D12

0: 0°C (default)

1: 32°C

D11

0: 0°C (default)

1: 16°C

D10

0: 0°C (default)

1: 8°C

0: 0°C (default)

1: 4°C

0: 0°C (default)

1: 2°C

0: 0°C (default)

1: 1°C

0: 0°C (default)

1: 0.5°C

0: 0°C (default)

1: 0.25°C

0: 0°C (default)

1: 0.125°C

[D3:D0]

Reserved

Current Sensor (ISENSEx) Low Limit Registers (Register 0x28

to Register 0x2B)

These read/write 16-bit registers set the low limits for the four

current sensor channels.

Table 63. VINx and Current Sensor Low Limit Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

[D3:D0]

B11

B10

Reserved

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