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AD7293 Datasheet(PDF) 76 Page - Analog Devices

Part # AD7293
Description  12-Bit Power Amplifier Current Controller
PDF  78 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7293 Datasheet(HTML) 76 Page - Analog Devices

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AD7293
Data Sheet
Rev. B | Page 76 of 78
Figure 59. Typical Power Amplifier Control Application
DEPLETION MODE AMPLIFIER BIASING AND
PROTECTION
Depletion mode devices (for example, gallium nitride (GaN) or
gallium arsenide (GaAs)) require temperature compensated
gate biasing voltages similar to enhancement mode devices (for
example, laterally diffused metal oxide semiconductor (LDMOS))
to maintain constant quiescent drain current with temperature.
The most important consideration for a depletion mode device
is the biasing sequence. If the gate of a depletion mode device is
at 0 V and the drain voltage is applied, the device may be
damaged by drawing excessive current. It is also likely that a
device may become potentially unstable at lower drain source
voltages. Therefore, decreasing the gate voltage to less than the
pinch off voltage while the drain voltage is being powered on
and off is necessary.
The AD7293 was designed for depletion mode power amplifier
biasing. Bipolar DAC outputs enable negative voltage biasing of
the gate on the depletion mode device. A closed-loop mode
combined with a low temperature drift reference ensures that
the loop is steady over temperature.
The AD7293 works to ensure that instability or destruction of
the depletion mode device is avoided. A PA_ON signal allows
the user the option to control an external PMOS switch to turn
on and off the drain current. This signal is set to the off state on
power-up. Because depletion mode devices require a negative
bias to remain at an acceptable level, and bipolar DACs transmit
on the AVSS supply for proper operation, PA_ON can be triggered
when AVSS exceeds an acceptable level.
In the event of an AVDD voltage supply failure, the bipolar DACs
clamp to the AVSS supply (−5 V), which ensures that the PA
AVDD
VDRIVE
VIN0
VIN1
VIN2
VIN3
UNI-VOUT0
UNI-VOUT1
UNI-VOUT2
UNI-VOUT3
VCLAMP0
DAC
CLAMP
CONTROL
VCLAMP1
BI-VOUT3
BI-VOUT2
BI-VOUT1
BI-VOUT0
AVSS
DACVDD-UNI
DVDD
VREFOUT
REFADC
MUX
PAVDD
PA_ON
VREFIN
1
D1–
D0–
D1+
D0+
DACVDD-BI
BIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
1
2
×
1.25V
RS3–
RS3+
RS2–
RS2+
RS1–
RS1+
–
–
+
+
BIPOLAR
DAC
BIPOLAR
DAC
BIPOLAR
DAC
RS0–
RS0+
2.5V
PMOS
CONTROL
SPI
INTERFACE
DIGITALI/Os
ALERT AND LIMIT
REGISTERS
CONTROL
LOGIC
1
AD7293
RESET
LOGIC
BI-VOUT0MON
BI-VOUT1MON
BI-VOUT2MON
BI-VOUT3MON
FILTER
RFOUT
GaN
RFIN
RSENSE
FILTER
RFOUT
GaN
RFIN
RSENSE
FILTER
RFOUT
GaN
RFIN
RSENSE
FILTER
RFOUT
GaN
RFIN
RSENSE
VPP
GAIN
CONTROL
GAIN
CONTROL
GAIN
CONTROL
GAIN
CONTROL
Rx POWER
MONITOR
Tx POWER
MONITOR
PRECISION
2.5V
REFERENCE
–
+
–
+



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