AD7293 datasheet(26/78 Pages) AD

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AD7293

Data Sheet

Rev. B | Page 26 of 78

PMOS Drain Switch Control

The AD7293 PA_ON output pin is capable of driving an

external PMOS switch. This external PMOS turns on or off the

drain current to a PA field effect transistor (FET). The PA_ON

output pin controls the device during power-up and power-down.

This feature can also be used as a protection feature when an

alert condition is detected because ALERT0 alerts or an AVSS or

AVDD supply failure can be used to trigger the PA_ON pin.

PAVDD determines the maximum voltage at the output of the

PA_ON pin. The off state is equal to PAVDD while the on state is

equal to AGND. The default state of the PA_ON signal is off.

Figure 45. PMOS Drain Switch Control

REFERENCE

The AD7293 has one high performance, 2.5 V on-chip reference

accessed via the VREFOUT pin. Noise performance can be improved

by the addition of a 10 nF capacitor between the VREFOUT pin and

the AGND pin. Connect VREFOUT to the VREFIN pin to use the

on-chip reference of the AD7293. An internal amplifier attenu-

ates to the ADC core, making the voltage at the ADC, REFADC =

1.25 V, half of VREFIN = 2.5 V. Use the REFADC pin for measurement

purposes only.

A 220 nF capacitor is required on the REFADC pin and must be

placed as close to the AD7293 as possible with no vias. The

internal reference typically requires 20 ms to power up and settle

when using a 220 nF decoupling capacitor on the REFADC pin.

Buffer the internal reference before it is used by external circuitry.

The AD7293 can also operate with an external reference of

2.5 V connected to the VREFIN pin.

If using an external reference, select a low temperature coefficient

specification, such as the ADR4525, to reduce the temperature

dependence of the system output voltage on ambient conditions.

VDRIVE FEATURE

The AD7293 also has a VDRIVE feature that controls the voltage at

which the SPI operates. Connect the VDRIVE pin to the supply to

which the SPI bus is pulled. The VDRIVE pin sets the input and

output threshold levels for the digital logic pins. The VDRIVE

feature allows the AD7293 to interface with 1.8 V, 3.3 V, and 5 V

processors.

OPEN-LOOP MODE

In open-loop mode, the default mode of operation, the current

sense amplifiers and bipolar DACs operate independently.

CLOSED-LOOP MODE

Alternatively, the AD7293 current sensors and bipolar DACs

can operate as four independent closed-loop drain current

controllers (closed-loop mode).

In closed-loop operation, the drain current through the PA FET

is set and automatically maintained by the PA controller through a

regulation circuit that includes the DAC and current sense moni-

tor. The control loop sets the PA bias current and continuously

maintains a constant voltage across the sense resistor (VSENSE =

ISENSE × RSENSE). When the DAC current updates, the closed-loop

adjusts the gate voltage of the PA until the drain current matches

the corresponding DAC code. The continuous regulation of the

loop compensates for variations of the PA threshold or voltage

drop on the LPF due to the PA gate current. The integrator

leads to a smooth transition on the output of the pin.

Figure 46. Closed-Loop Control

Each of the four current closed loops consists of a DAC, an

error amplifier, and an integrator in the forward path to drive

the gate of the PA FET. A high-side current sense amplifier in

the feedback path senses that PA drain bias current and closes

the loop.

An external gate filter can be introduced between the gate of the

power amplifier and the integrator output pins when operating

in closed-loop mode to limit the noise bandwidth and to ensure

PA stability. The gate filter time constant (τG) must be between

5 µs and 50 µs.

Adjustable Closed-Loop Setpoint Ramp Time

The transition between two successive setpoints of the DAC are

interpolated in a linear manner with the aid of a ramp generator.

When moving to a new closed-loop setpoint, limiting the rate of

change of the drain current is often required. To facilitate this,

the AD7293 can automatically generate a linear ramp between

the old and new DAC settings, over a programmable duration.

Write to the ramp time register to enable this feature, which

allows ramp times of between 4 ms and 31.75 ms to generate,

programmable in 250 µs steps. If a value of less than 4 ms is

written to the register, the ramp generator disables, and the new

PAVDD

PA_ON

PMOS

CONTROL

RSENSE

V p-p

PMOS

DRAIN

SWITCH

RSx+

RSx–

CURRENT

SENSOR

PA FET

FILTER

RF IN

RF OUT

RSx+

RSx–

LPF

BIPOLAR

DAC

(PROGRAMMABLE

RAMP TIME)

AD7293

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