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IP200 Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers |
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IP200 Datasheet(HTML) 21 Page - List of Unclassifed Manufacturers |
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21 / 30 page ![]() Phone: +49 371 33 77 - 0 Fax:: +49 371 33 77 272 Internet: www.gemac-chemnitz.de Email: interpolation@gemac-chemnitz.de sales@gemac-chemnitz.de GEMAC Gesellschaft für Mikroe lektronikanwendung Chemnitz mbH Zwickauer Straße 227 D-09116 Chemnitz, Germany Date: 20.04.04 Page 21 of 30 Title: Data Sheet GC-IP200 Name of Document: 43500-DB-2-1-E-IP200.pdf 8 Error Processing The IP200 has 6 sources for generating the global error signal. Each source can be activated by the corresponding bit in the error mask register. With the LatchErr bit being activated, the individual error signals are stored until the next chip reset or until the next SPI ResetCount command (command 0x01) occurs, respectively. The logic OR function of the masked and stored error signals appears as a low active signal on pin NERR. With the HoldErr bit being active, the A, B and OREF outputs freeze in the current state on error case. The NERR and NRES pins can be shorted in order to re-synchronise the IC in the event of an error. The error signal is active for 8 system clocks in this case. Error Mask Register Bit Description (if bit is set) GCOMP Gain controller reaches his limit OCOMP Offset controller reaches his limit BQLOW Amplitude Error: the resulting Sine-Cosine-Vector is to small ADUOVL One or both ADC-Converter are clipping FAST1 Signal frequency to high, no signal direction recognition possible (SPEED=1), Signal frequency to fast for proper generating A/B/OREF - Signals (SPEED=0) FAST2 Signal frequency to fast for proper generating the A/B/OREF - Signals (depends upon IT(2:0) , refer also to table “Clock Frequency Examples” in chapter 4.4) HoldErr The A/B/OREF - Signals freeze in error case LatchErr The masked error signal is stored until next SPI-reset-command or a global reset occurs, respectively For square wave operation (A/B-Signals) it is recommended to set the error mask register to 0x3F or 0xFF respectively, in counter mode use the error mask register loaded with 0xDF and set the SPEED bit in the CFG0 register. The status register STAT contains all error bits. The MVAL and CNT register contain logic combinations of counter relevant error bits: SENSERR = ADUOVL or BQLOW or OCOMP or GCOMP AMPERR = ADUOVL or BQLOW Sensor breakage error: Partial or complete tearing off of the connected sensor is detected in the IP200 at the time of occurrence. Thereafter, the automatic gain-offset-controller tries to compensate this error which, due to the large operating range of the gain-offset-controller, can lead to a situation where the cause of this error seems to have been eliminated. |
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