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Date: 20.04.04

Page 23 of 30

Title:

Data Sheet GC-IP200

Name of Document:

43500-DB-2-1-E-IP200.pdf

9.3

Configuration Bits Defaults

Name

Description

Default

IR(2:0)

Interpolation Rate

Pin IR(2:0)is read

IT(2:1)

Interval Time

Pin IT(2:1)is read

IT(0)

Interval Time

0

GFE

Glitch-Filter-Enable

Pin TRG/GFE is read

SPEED

Speed-Mode for internal Counter

Pin SDI/SPEED is read

DISREG

Disable automatic controller

0

DISREF

Disable Index Point

0

TRSLP

Trigger Edge

0

TSTSTRB

Enable Strobe-Signal on pin OREF

0

ERRMASK

Error Mask Register

0x3F

SGAIN

Initial value Gain Correction, Sine

0x80

SOFF

Initial value Offset Correction, Sine

0x00

CGAIN

Initial value Gain Correction, Cosine

0x80

COFF

Initial value Offset Correction, Cosine

0x00

SYNC

SPI synchronisation with internal

sequential control counter

0x00

10 Signal Propagation Time

The delay time between the sampling point of the analogue input signals (sine/cosine) and the availability of

the interpolation result (i.e. related to trigger) totals 90 system clocks. The delay time between sampling and

updating the data registers and those values available via parallel or serial interface, respectively, totals 96

system clocks. If a external counter unit connected to the A/B/OREF outputs is used, the time between

sampling and output of resulting square waves totals 122 system clocks.

Every 32nd system clock a new measurement result appears on the parallel data output. Note that the data

transferring time of the used interface is added to the IP200 internal system propagation time.

N

Sample s(t)

N

N+1

N+2

N+3

N+4

N+5

N+6

ADC-Data

N+1

N+2

N+3

N+4

N-2

N-1

N

N+1

N+2

N-2

N-1

N+1

N+2

DATA Register SPI / Parallel

Trigger Event Result

N-1

N-3

N-3

32x SYSCLK

ext. counter unit con. to A/B

N

X(N-3)

X(N-4)

X(N-1)

X(N-1)-1

X(N-1)+1

X(N-1)+2

X(N-1)+3

A

B

Index Point

Index Point:

OREF is H

X(N-2)

X(N-1)

X(N)

X(N+1)

X(N+2)

26x SYSCLK

Figure 14



Note that the constant delay time of the IC (as with any other digital signal processing systems)

result in a frequency-dependent phase shift between the analogue input signals and the output

signals (d

 = 2·f·t