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D-09116 Chemnitz, Germany

Date: 20.04.04

Page 9 of 30

Title:

Data Sheet GC-IP200

Name of Document:

43500-DB-2-1-E-IP200.pdf

4.2

Error Signal

An error signal is generated if the input signals are no longer plausible. The error signal is also generated if

the input frequency is so high that the square-wave signals are unable to follow, and/or when the maximum

input frequency is exceeded. The evaluation of the internal error sources is activated via an error mask

register. The response of the square-wave outputs in the event of an error can also be configured via this

register. The NERR and NRES pins can be connected in order to start a re-synchronisation process of the IC

in the event of an error.



If the error signal was activated, and/or if one of the error bits was set in the result register, the present

measuring result and all the following results must be discarded. Following elimination of the cause of the

error and a reset of the error bit, the reference point must once again be passed by for absolute value

measurements!

4.3

Interpolation Rate

The interpolation rate can be set at 200, 160, 100, 80, 50, 40, 25 and 20. The interpolation rate as defined

for the purposes of this application is the number of increments into which one sine period of the input signal

is divided. This also corresponds to the number of edge changes on the A/B output signals per input signal

period. This means that the number of square-wave periods at the A and B outputs totals 1/4 of the

interpolation rate per input signal period.



In the event that a standard interpolation counter or quadrature decoder is connected to the A/B outputs, this

must work in "quadruple evaluation" mode in order to achieve the full interpolation rate.

4.4

Interval Time / Maximum Input Frequency

In counter mode (the SPEED Bit in the CFG0 Register being set), the maximum input frequency totals

distance at the output, where:

Clock frequency at Pin XA

IR

:

Activated Interpolation Rate

IT

:

Activated Interval Time

The limit values are a maximum input frequency of aprox. 400kHz with a clock frequency of 40MHz on the

one hand, as well as a guaranteed edge distance of 128µs at the A/B signals with a clock frequency of 1MHz

on the other. Between these two limits, a large number of specific systems can be adapted by selecting a

suitable clock frequency and interval time of the IP200.



These values apply on condition of an adjusted phase between the input signals and a steady state of the

internal gain-offset-controller. Until this time, the input frequency must not exceed 50% of the specified

maximum frequency.