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Date: 20.04.04

Page 14 of 30

Title:

Data Sheet GC-IP200

Name of Document:

43500-DB-2-1-E-IP200.pdf

5.3

Parallel Data Port

This interface outputs the last activated SPI read register synchronized to the IP200 internal sequential

control counter. The appearing data are separated into two 16-bit words. After reset, the data of the SPI read

register address 0x00(MVAL)appears on DATA(15:0) by default.

D(31:16)

D(31:16)

D(15:0)

30

Sequential

Control Counter

29

DATA(15:0)

OUTHIGH

31

0

1

14

13

15

16

17

STRB

XA

Signal

Figure 12

To reduce switching noise on the data port the Data outputs DATA(15:8) will be switched 1 clock cycle after

the outputs DATA(7:0). That's why the value at DATA(15:8) is undefined in the clock cycles 0 and 16.

For external components the edges of OUTHIGH can be used to register the new valid data. The level on

OUTHIGH

show, which part of the 32-bit read value is active on the data pins (either LSB or MSB). A optional

Strobe-Signal (on pin OREF) can be activated via TSTRB bit in the configuration register TSTCFG.



To get out a desired read register on parallel port, it is necessary to read this register via serial interface first.

EVERY other SPI access at any time can change the behaviour of parallel port.

If the parallel interface be used solely as output port, please select carefully the corresponding attachment

circuit of the configuration and the double function pins at the IP200. Please refer also application notes in

the document 4300x-AN-3-0-E-IPx.pdf.