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Date: 20.04.04

Page 22 of 30

Title:

Data Sheet GC-IP200

Name of Document:

43500-DB-2-1-E-IP200.pdf

9

Reset / Configuration

The IP200 IC does not contain an internal Power-On-Reset circuit! It is essential to supply the IP200

with an external reset signal on pin NRES. This reset signal must appear low until 3ms after VDD rising to a

voltage level of 4.75V.

If NRES and NERR are shorted, the error signal is hel

d through the “NERR -chain” while one of the chain flip-

flops contains a “0”.

NRES

Reset (LOW-active) to

all Flip Flops in the IC

NRES

CLK

internal NERR

D

Q

CLK

D

Q

NERR

VDD

Chain of Flip Flops,

not affected by NRES-Signal

IP200

Figure 13

9.1

Reset Processing

1.

Pin SDO/RDY goes to L, all register will be initialised with default values.

2.

The IC is operating a self-calibration, the configuration pins are read into the CFG0 register.

3.

Start of normal operation.

4.

Pin SDO/RDY goes to H (external pull-up required).

5.

The configuration register could be changed via SPI interface.

The time between the rising edge of NRES and the rising edge of SDO/RDY, which means the end of the

reset process, amount to approximately 1365 system clocks.

9.2

Configuration

There are two different types of configuration possible:

Configuration via input pins

 The register CFG0 will be configured via the input pins IR(2:0), IT(2:1), TRG/GFE and

SDI/SPEED

.

 All other registers are initialised with default values.

 Suitable for low-cost single-chip and standard applications.

Configuration via SPI

 Pins DP(3:0) select SPI hardware address (for multi-channel systems only).

 Suitable for applications with SPI interface, for example microcontroller systems.