Phone:

+49 371 33 77 - 0

Fax::

+49 371 33 77 272

Internet:

www.gemac-chemnitz.de

Email:

interpolation@gemac-chemnitz.de

sales@gemac-chemnitz.de

GEMAC

Gesellschaft für

Mikroe lektronikanwendung Chemnitz mbH

Zwickauer Straße 227

D-09116 Chemnitz, Germany

Date: 20.04.04

Page 26 of 30

Title:

Data Sheet GC-IP200

Name of Document:

43500-DB-2-1-E-IP200.pdf

12 Mechanical Characteristics

12.1

Pinout

Pin Name

Type

Description

Pin Name

Type

Description

1

DATA(0)

COUT

Data Output Port

33

SINP

AIN

Positive Signal Input Sine

2

DATA(1)

COUT

Data Output Port

34

SINN

AIN

Negative Signal Input Sine

5)

3

DATA(2)

COUT

Data Output Port

35

OUTS180 AOUT

Sine Analogue Output (Phase rev.)

4

DATA(3)

COUT

Data Output Port

36

OUTS

AOUT

Sine Analogue Output

5

DATA(4)

COUT

Data Output Port

37

INPS

AIN

ADC Input Sine

6

DATA(5)

COUT

Data Output Port

38

RSH

AIO

Pos. Reference Voltage SADC

7

DATA(6)

COUT

Data Output Port

39

RSL

AIO

Neg. Reference Voltage SADC

8

DATA(7)

COUT

Data Output Port

40

V0

AIO

Analogue Midscale Voltage

9

DATA(8)

COUT

Data Output Port

41

VSSA2

ASUP

Analogue Ground

10

DATA(9)

COUT

Data Output Port

42

VDDA2

ASUP

Analogue Supply

11

DATA(10)

COUT

Data Output Port

43

RCL

AIO

Neg. Reference Voltage CADC

12

DATA(11)

COUT

Data Output Port

44

RCH

AIO

Pos. Reference Voltage CADC

13

DATA(12)

COUT

Data Output Port

45

INPC

AIN

ADC Input Cosine

14

DATA(13)

COUT

Data Output Port

46

OUTC

AOUT

Cosine Analogue Output

15

DATA(14)

COUT

Data Output Port

47

COSN

AIN

Negative Signal Input Cosine

5)

16

DATA(15)

COUT

Data Output Port

48

COSP

AIN

Positive Signal Input Cosine

17

VSS2

DSUP

Digital Ground

49

PH

AIN

Analogue Phase Correction Input

5)

18

VDD2

DSUP

Digital Supply

50

VDDA3

ASUP

Analogue Supply

19

OUTHIGH

COUT

MSB at Parallel Data Port active

51

VSSA3

ASUP

Analogue Ground

20

CLRTRG

TTLIN

Clear Trigger

1)

52

IT2

TTLIN

Interval Time Select 3

3)

21

XB

OSC

Crystal Input B

1)

53

IT1 / DP3

TTLIN

IT Select 1 / DProg 3

3)

22

XA

OSC

Crystal Input B / ext. Clock

54

IR2 / DP2

TTLIN

Interpolation Rate / DProg 2

3)

23

SCLK

TTLIN

SPI Clock

3)

55

IR1 / DP1

TTLIN

Interpolation Rate / DProg 1

3)

24

SCEN

TTLIN

SPI Enable

2)

56

IR0 / DP0

TTLIN

Interpolation Rate / DProg 0

3)

25

SDI / SPEED

TTLIN

SPI Data Input/ SPEED (Cfg)

1)

57

OREF

COUT

Index Point Output Signal

26

SDO/RDY

CODO

SPI Data Output

4)

58

B

COUT

Square Wave Output B

27

VDD3

DSUP

Digital Supply

59

A

COUT

Square Wave Output A

28

TM

TTLIN

Test Mode Input

1)

60

TRG/GFE TTLIN

Trigger / Glitch-Filter-Enable

3)

29

VSSA1

ASUP

Analogue Ground

61

NERR

ODPU

Error Output

30

VDDA1

ASUP

Analogue Supply

62

NRES

TTLIN

Reset

31

REFN

AIN

Negative Reference Input

6)

63

VDD1

DSUP

Digital Supply

32

REFP

AIN

Positive Reference Input

6)

64

VSS1

DSUP

Digital Ground

COUT

CMOS - OUT 4mA

CODO

CMOS - OUT 4mA / Open-Drain

ODPU

CMOS - OUT 4mA / Open-Drain /w Pull Up

ODPD

CMOS - OUT 4mA / Open-Drain /w Pull Down

TTLIN

Input, TTL - Level

OSC

Oscillator - I/O, 6pF

AIN / AOUT / AIO

Analogue-IO

DSUP

Digital Power Supply

ASUP

Analogue Power Supply

6)

if unused, pull the REFP and REFN inputs to different analogue voltage levels. The absolute voltage

difference between these pins must exceed the maximum reference comparator input hysteresis range for a

comparator safety behaviour



Each IC input pin requires a defined connection!