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GS3470 Datasheet(PDF) 30 Page - Semtech Corporation |
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GS3470 Datasheet(HTML) 30 Page - Semtech Corporation |
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30 / 169 page ![]() GS3470 Final Data Sheet Rev.8 PDS-060500 September 2017 30 of 169 Semtech www.semtech.com 4.9.5.1 Delay Line The GS3470 has the ability to shift the Setup/Hold window on the receive interface, by using an on-chip delay line to shift the phase of PCLK with respect to the data bus. The timing of the PCLK output, relative to the data, can be adjusted through the host interface registers. Each data rate has its own 5-bit delay line offset setting as well as a PCLK invert option. The delay adjustment range is defined in Table 4-6. The PCLK output can be delayed by up to 0.5UI using the rate dependent PCLK_DELAY_XX parameters and it can be advanced by 0.5UI by using the PCLK_INVERT_XX parameters. HIGH LOW LOW LOW LOW LOW 20-bit data output 74.25 or 74.25/1.001MHz HIGH HIGH X HIGH LOW LOW 20-bit SD format 13.5MHz HIGH HIGH X LOW LOW LOW 20-bit data output 13.5MHz LOW LOW HIGH HIGH LOW X 10-bit multiplexed 3G DDR format 148.5 or 148.5/1.001MHz LOWLOW HIGH LOWLOW X 10-bit data output DDR format 148.5 or 148.5/1.001MHz LOW LOW LOW HIGH LOW LOW 10-bit multiplexed HD format 148.5 or 148.5/1.001MHz LOW LOW LOW LOW LOW LOW 10-bit data output 148.5 or 148.5/1.001MHz LOW LOW LOW HIGH LOW HIGH 10-bit multiplexed HD DDR format 74.25 or 74.25/1.001MHz LOW LOW LOW LOW LOW HIGH 10-bit data DDR format 74.25 or 74.25/1.001MHz LOW HIGH X HIGH LOW LOW 10-bit multiplexed SD format 27MHz LOW HIGH X LOW LOW LOW 10-bit data output 27MHz LOW HIGH X LOW HIGH LOW 10-bit ASI output 27MHz LOW HIGH X HIGH LOW HIGH 10-bit multiplexed SD DDR format 13.5MHz LOW HIGH X LOW LOW HIGH 10-bit data output DDR format 13.5MHz LOW HIGH X LOW HIGH HIGH 10-bit ASI output DDR format 13.5MHz Table 4-5: GS3470 Output Data Formats (Continued) Pin/CSR Bit Settings Output Data Format PCLK Rate 20BIT/ 10BIT SD/HD 3G/HD SMPTE_ BYPASS DVB-ASI SD_HD_ DDR_SEL |
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