GS3470 datasheet(9/169 Pages) SEMTECH

9 / 169 page

GS3470

Final Data Sheet

Rev.8

PDS-060500

September 2017

9 of 169

Semtech

www.semtech.com

Analog Input

Loop Filter component connection. Connect as per Typical

Application Circuit.

C4, D4

VCO_VDD

Power

Power pin for the VCO. Connect to RC filter as per Typical Application

Circuit. Connect to a 1.2V ±5% analog supply through a 24Ω ±1%

resistor. Additionally, connect to ground through a 10μF capacitor.

C7, D9, E4, F4, F5,

G4, G5, G9, J7, H8

CORE_GND

Power

Ground pins for digital circuitry. Connect to digital ground.

D3, E3, F2,

F3, G2, G3

A_GND

Power

Ground pins for analog circuitry. Connect to analog ground.

D1, E2

B1, B2

DDI1_VDD

DDI0_VDD

Power

Power pins for SDI buffer. Connect to 1.2V DC analog.

D6, D5, C6,

C5, B6, B5

STAT[5:0]

Digital Output

Multi-function status outputs. See Section 4.11 for more details on

assigning signals to STAT pins.

Please refer to the Output Logic parameters in Table 2-3: DC

Electrical Characteristics for logic level threshold and compatibility.

Each of the STAT[5:0] pins can be configured individually to output

one of the following signals.

See Table 4-7: Output Signals Available on Programmable

Multi-Function Pins for Status Signal Selection Codes and Default

Output Pins.

TRST

Digital Input,

Internal

Pull-down

JTAG interface reset. Digital active-low reset input. Used to reset the

JTAG test sequence.

When LOW, the JTAG test sequence is reset.

When HIGH, normal operation of the JTAG test sequence resumes.

TDI

Digital Input,

Internal Pull-up

JTAG interface Test Data Input. Serial instructions and data are

received on this pin.

E1, A3

CT[1:0]

Analog Input

Decoupling for internal SDI termination resistors. Connect as per

Typical Application Circuit. When an input is not used, its

corresponding CT pin can be left unconnected.

E5, E6, F6, G6

CORE_VDD

Power

Power connection for device core. Connect to 1.2V DC digital.

TDO

Digital Output

JTAG interface Test Data Output. TDO is the serial output for test

instructions and data.

TCK

Digital Input

JTAG interface Test Clock input. The test clock input provides the

clock for the test logic of this device.

TMS

Digital Input,

Internal Pull-up

JTAG interface Test Mode Select input. This signal is decoded by the

internal TAP controller to control test operations.

SDIN

Digital Input

Serial Digital Data Input for the Gennum Serial Peripheral Interface

(GSPI) host control/status port. When GSPI is not used, SDIN should

be tied HIGH or LOW to minimize noise.

SDOUT

Digital Output

Serial Digital Data Output for the Gennum Serial Peripheral Interface

(GSPI) host control/status port. Active-high output. When GSPI is not

used, leave unconnected.

Table 1-1: Pin Descriptions (Continued)

Pin Number

Name

Type

Description

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