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AD9175 Datasheet(PDF) 113 Page - Analog Devices

Part # AD9175
Description  Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
PDF  150 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9175 Datasheet(HTML) 113 Page - Analog Devices

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Data Sheet
AD9175
Rev. A | Page 113 of 150
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x281
PLL_STATUS
[7:1]
RESERVED
Reserved.
0x0
R
0
SERDES_PLL_LOCK
PLL is locked when this bit is high.
0x0
R
0x300
GENERAL_JRX_
CTRL_0
[7:4]
RESERVED
Reserved.
0x0
R
3
LINK_MODE
Reads back 0 when in single-link mode and
1 when in dual-link mode.
0x0
R/W
2
LINK_PAGE
Link paging. This bit selects which link
register map is used. This paging affects
Register 0x400 to Register 0x4BB.
0x0
R/W
0
Page QBD0 for Link 0.
1
Page QBD1 for Link 1.
[1:0]
LINK_EN
These bits bring up the JESD204B digital
receiver when all link parameters are
programmed and all clocks are ready. Bit 0
applies to Link 0, whereas Bit 1 applies to
Link 1. Link 1 is only available in dual-link
mode.
0x0
R/W
0x302
DYN_LINK_
LATENCY_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DYN_LINK_
LATENCY_0
Dynamic link latency, Link 0. Latency
between the LMFC receiver for Link 0 and
the last arriving LMFC boundary in units of
PCLK cycles.
0x0
R
0x303
DYN_LINK_
LATENCY_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DYN_LINK_
LATENCY_1
Dynamic link latency, Link 1. Latency
between the LMFC receiver for Link 1 and
the last arriving LMFC boundary in units of
PCLK cycles.
0x0
R
0x304
LMFC_DELAY_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_DELAY_0
LMFC delay, Link 0. Delay from the LMFC to
the LMFC receiver for Link 0 in units of PCLK
cycles.
0x0
R/W
0x305
LMFC_DELAY_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_DELAY_1
LMFC delay, Link 1. Delay from the LMFC to
the LMFC receiver for Link 1 in units of PCLK
cycles.
0x0
R/W
0x306
LMFC_VAR_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_VAR_0
Variable delay buffer, Link 0. These bits set
when data is read from a buffer to be con-
sistent across links and power cycles (in
units of PCLK cycles). The maximum value is
0xC.
0x3F
R/W
0x307
LMFC_VAR_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_VAR_1
Variable delay buffer, Link 1. These bits set
when data is read from a buffer to be con-
sistent across links and power cycles (in
units of PCLK cycles). The maximum value is
0xC.
0x3F
R/W
0x308
XBAR_LN_0_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:3]
LOGICAL_LANE1_
SRC
Logical Lane 1 source. These bits select a
physical lane to be mapped onto Logical
Lane 1.
0x1
R/W
000
Data is from SERDIN0±.
001
Data is from SERDIN1±.
010
Data is from SERDIN2±.
011
Data is from SERDIN3±.
100
Data is from SERDIN4±.
101
Data is from SERDIN5±.
110
Data is from SERDIN6±.



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