AD9175 datasheet(112/150 Pages) AD

112 / 150 page

AD9175

Data Sheet

Rev. A | Page 112 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x247

EQ_FB_PHY_3

[7:5]

RESERVED

Reserved.

0x0

[4:0]

EQ_PHY3

SERDES equalizer setting for PHY3. Set this

control to 0x1F for optimal performance.

0x19

R/W

0x248

EQ_FB_PHY_4

[7:5]

RESERVED

Reserved.

0x0

[4:0]

EQ_PHY4

SERDES equalizer setting for PHY4. Set this

control to 0x1F for optimal performance.

0x19

R/W

0x249

EQ_FB_PHY_5

[7:5]

RESERVED

Reserved.

0x0

[4:0]

EQ_PHY5

SERDES equalizer setting for PHY5. Set this

control to 0x1F for optimal performance.

0x19

R/W

0x24A

EQ_FB_PHY_6

[7:5]

RESERVED

Reserved.

0x0

[4:0]

EQ_PHY6

SERDES equalizer setting for PHY6. Set this

control to 0x1F for optimal performance.

0x19

R/W

0x24B

EQ_FB_PHY_7

[7:5]

RESERVED

Reserved.

0x0

[4:0]

EQ_PHY7

SERDES equalizer setting for PHY7. Set this

control to 0x1F for optimal performance.

0x19

R/W

0x250

LBT_REG_CNTRL_0

[7:0]

EN_LBT_DES_

RC_CH

Enable loopback test for desired physical

lanes per PHY, with Bit x corresponding to

PHY x.

0x0

R/W

0x251

LBT_REG_CNTRL_1

[7:2]

RESERVED

Reserved.

0x0

EN_LBT_

HALFRATE_DES_

Enables half rate mode for the loopback

test. If this bit is set to 1, the output data

rate = 2× the input clock frequency. If this

bit is set to 0, the output data rate = the

input clock frequency.

0x1

R/W

INIT_LBT_SYNC_

DES_RC

Initiate the loopback test by toggling this

bit from 0 to 1, then back to 0.

0x0

R/W

0x253

SYNCOUT0_CTRL

[7:1]

RESERVED

Reserved.

0x0

R/W

SEL_SYNCOUT0_

MODE

This control determines the output driver

mode for the SYNCOUT0± pin operation.

Both SYNCOUT0± and SYNCOUT1± must be

set to the same mode of operation.

0x0

R/W

SYNCOUT0± is set to CMOS output.

SYNCOUT0± is set to LVDS output.

0x254

SYNCOUT1_CTRL

[7:1]

RESERVED

Reserved.

0x0

R/W

SEL_SYNCOUT1_

MODE

This control determines the output driver

mode for the SYNCOUT1± pin operation.

Both SYNCOUT0± and SYNCOUT1± must be

set to the same mode of operation.

0x0

R/W

SYNCOUT1± is set to CMOS output.

SYNCOUT1± is set to LVDS output.

0x280

PLL_ENABLE_CTRL

[7:3]

RESERVED

Reserved.

0x0

LOLSTICKYCLEAR_

LCPLL_RC

Clears out loss of lock bit.

0x0

R/W

LDSYNTH_LCPLL_

Pulse high to start VCO calibration (without

restarting the regulator or remeasuring the

temperature).

0x0

R/W

SERDES_PLL_

STARTUP

SERDES circuitry blocks are powered off

when this bit is set to 0. Set this bit to 1 at

the end of the SERDES configuration writes.

When this bit is set to 1, it powers up the

SERDES PLL blocks and starts the LDO and

calibration routine to lock the PLL auto-

matically to the appropriate lane rate based

on the JESD204B mode and interpolation

options programmed in the device. The

SERDES_PLL_LOCK bit (Register 0x281,

Bit 0) reads 1 when the PLL achieves lock.

0x1

R/W

AD9175 Datasheet(PDF) 112 Page - Analog Devices

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