AD9175 datasheet(129/150 Pages) AD

129 / 150 page

Data Sheet

AD9175

Rev. A | Page 129 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x476

CTRLREG1

[7:5]

RESERVED

Reserved.

0x0

QUAL_RDERR

Error reporting behavior for concurrent not

in table (NIT) and running disparity (RD)

errors. This control is paged by the

LINK_PAGE control in Register 0x300. Set

this bit to 1. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x1

R/W

NIT has no effect on RD error.

NIT error masks concurrent with RD error.

[3:1]

RESERVED

Reserved.

0x0

R/W

FCHK_N

Checksum calculation method. This control

is paged by the LINK_PAGE control in

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0

R/W

Checksum is calculated by summing the

individual fields in the link configuration

table as defined in Section 8.3, Table 20 of

the JESD204B standard.

Checksum is calculated by summing the

registers containing the packed link

configuration fields (sum of Register 0x450

to Register 0x45A, modulo 256).

0x477

CTRLREG2

ILS_MODE

Data link layer test mode is enabled when

this bit is set to 1. CGS pattern is followed

by a perpetual ILAS sequence. This control

is paged by the LINK_PAGE control in

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0

R/W

Normal mode.

CGS pattern is followed by a perpetual ILAS

sequence.

RESERVED

Reserved.

0x0

R/W

REPDATATEST

Repetitive data test enable using the JTSPAT

pattern. To enable the test, Bit 7 of this

the LINK_PAGE control in Register 0x300. This

signal must only be programmed while the

QBD is held in soft reset (Register 0x475, Bit

3), and must not be changed during normal

operation.

0x0

R/W

QUETESTERR

Queue test error mode. This control is

paged by the LINK_PAGE control in Register

0x300. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0x0

R/W

When this bit = 0, simultaneous errors on

multiple lanes are reported as one error.

Selected when this bit = 1 and when

REPDATATEST = 1. Detected errors from all

lanes are trapped in a counter and

sequentially signaled on SYNCOUTx±.

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