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AD9175 Datasheet(PDF) 133 Page - Analog Devices |
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AD9175 Datasheet(HTML) 133 Page - Analog Devices |
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133 / 150 page  Data Sheet AD9175 Rev. A | Page 133 of 150 Addr. Name Bits Bit Name Settings Description Reset Access [2:0] ECNT_TCH0 Terminal count hold enable of error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: 0x7 R/W Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x489 ECNT_TCH1 [7:3] RESERVED Reserved. 0x0 R [2:0] ECNT_TCH1 Terminal count hold enable of error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: 0x7 R/W Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x48A ECNT_TCH2 [7:3] RESERVED Reserved. 0x0 R [2:0] ECNT_TCH2 Terminal count hold enable of error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: 0x7 R/W Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x48B ECNT_TCH3 [7:3] RESERVED Reserved. 0x0 R [2:0] ECNT_TCH3 Terminal count hold enable of error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: 0x7 R/W |
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