AD9175 datasheet(137/150 Pages) AD

137 / 150 page

Data Sheet

AD9175

Rev. A | Page 137 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[2:0]

ECNT_TCR5

Terminal count reached indicator of error

counters for Lane 5. This control is paged by

the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the user;

otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x496

ECNT_STAT6

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA6

This output indicates if Lane 6 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

[2:0]

ECNT_TCR6

Terminal count reached indicator of error

counters for Lane 6. This control is paged by

the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the user;

otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x497

ECNT_STAT7

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA7

This output indicates if Lane 7 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

[2:0]

ECNT_TCR7

Terminal count reached indicator of error

counters for Lane 7. This control is paged by

the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the user;

otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x4B0

LINK_STATUS0

BDE0

Bad disparity errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

Error count < ETH[7:0] value.

Error count ≥ ETH[7:0] value.

NIT0

Not in table errors status for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300.

0x0

Error count < ETH[7:0] value.

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