AD9175 datasheet(135/150 Pages) AD

135 / 150 page

Data Sheet

AD9175

Rev. A | Page 135 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[2:0]

ECNT_TCH7

Terminal count hold enable of error

counters for Lane 7. This control is paged by

the LINK_PAGE control in Register 0x300.

When set, the designated counter is to hold

the terminal count value of 0xFF when it is

reached until the counter is reset by the

user. Otherwise, the designated counter

rolls over. Counters of each lane are

addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register

0x475, Bit 3), and must not be changed

during normal operation.

0x490

ECNT_STAT0

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA0

This output indicates if Lane 0 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

[2:0]

ECNT_TCR0

Terminal count reached indicator of error

counters for Lane 0. This control is paged by

the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the user;

otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x491

ECNT_STAT1

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA1

This output indicates if Lane 1 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

[2:0]

ECNT_TCR1

Terminal count reached indicator of error

counters for Lane 1. This control is paged by

the LINK_PAGE control in Register 0x300.

Set these bits to 1 when the corresponding

counter terminal count value of 0xFF is

reached. If ECNT_TCHx is set, the terminal

count value for the corresponding counter

is held until the counter is reset by the user;

otherwise, the counter rolls over and

continues counting. Counters of each lane

are addressed as follows:

0x0

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x492

ECNT_STAT2

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA2

This output indicates if Lane 2 is enabled.

This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

AD9175 Datasheet(PDF) 135 Page - Analog Devices

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