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AD9175 Datasheet(PDF) 134 Page - Analog Devices

Part # AD9175
Description  Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
PDF  150 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9175 Datasheet(HTML) 134 Page - Analog Devices

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AD9175
Data Sheet
Rev. A | Page 134 of 150
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
Bit 2 = unexpected K character error (UEK).
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be programmed while
the QBD is held in soft reset (Register
0x475, Bit 3), and must not be changed
during normal operation.
0x48C
ECNT_TCH4
[7:3]
RESERVED
Reserved.
0x0
R
[2:0]
ECNT_TCH4
Terminal count hold enable of error
counters for Lane 4. This control is paged by
the LINK_PAGE control in Register 0x300.
When set, the designated counter is to hold
the terminal count value of 0xFF when it is
reached until the counter is reset by the
user. Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K character error (UEK).
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be programmed while
the QBD is held in soft reset (Register
0x475, Bit 3), and must not be changed
during normal operation.
0x48D
ECNT_TCH5
[7:3]
RESERVED
Reserved.
0x0
R
[2:0]
ECNT_TCH5
Terminal count hold enable of error
counters for Lane 5. This control is paged by
the LINK_PAGE control in Register 0x300.
When set, the designated counter is to hold
the terminal count value of 0xFF when it is
reached until the counter is reset by the
user. Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K character error (UEK).
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be programmed while
the QBD is held in soft reset (Register
0x475, Bit 3), and must not be changed
during normal operation.
0x48E
ECNT_TCH6
[7:3]
RESERVED
Reserved.
0x0
R
[2:0]
ECNT_TCH6
Terminal count hold enable of error
counters for Lane 6. This control is paged by
the LINK_PAGE control in Register 0x300.
When set, the designated counter is to hold
the terminal count value of 0xFF when it is
reached until the counter is reset by the
user. Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K character error (UEK).
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be programmed while
the QBD is held in soft reset (Register
0x475, Bit 3), and must not be changed
during normal operation.
0x48F
ECNT_TCH7
[7:3]
RESERVED
Reserved.
0x0
R



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