AD9175 datasheet(130/150 Pages) AD

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AD9175

Data Sheet

Rev. A | Page 130 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

AR_ECNTR

Automatic reset of error counter. The error

counter that causes assertion of

SYNCOUTx± is automatically reset to 0

when AR_ECNTR = 1. All other counters are

unaffected. This control is paged by the

LINK_PAGE control in Register 0x300. This

signal must only be programmed while the

QBD is held in soft reset (Register 0x475, Bit

3), and must not be changed during normal

operation.

0x0

R/W

[2:0]

RESERVED

Reserved.

0x0

0x478

KVAL

[7:0]

KSYNC

Number of 4 × K multiframes during ILAS.

This control is paged by the LINK_PAGE

control in Register 0x300. This signal must

only be programmed while the QBD is held

in soft reset (Register 0x475, Bit 3), and

must not be changed during normal

operation.

0x1

R/W

0x47C

ERRORTHRES

[7:0]

ETH

Error counter threshold value. These bits set

when a SYNCOUTx± error or IRQx interrupt

is sent due to BD, NIT, or UEK errors. This

control is paged by the LINK_PAGE control

in Register 0x300. This signal must only be

programmed while the QBD is held in soft

reset (Register 0x475, Bit 3), and must not

be changed during normal operation.

0xFF

R/W

0x47D

SYNC_ASSERT_

MASK

[7:3]

RESERVED

Reserved.

0x0

[2:0]

SYNC_ASSERT_

MASK

SYNCOUTx± assertion enable mask for BD,

NIT, and UEK error conditions. This control is

paged by the LINK_PAGE control in Register

0x300. Active high, SYNCOUTx±assertion

enable mask for BD, NIT, and UEK error

conditions, respectively. When an error

counter, in any lane, has reached the error

threshold count, ETH[7:0], and the

corresponding SYNC_ASSERT_MASK bit is

set, SYNCOUTx± is asserted. The mask bits

are as follows (the bit sequence is reversed

with respect to the other error count

controls and the error counters):

0x7

R/W

Bit 2 = bad disparity error (BDE).

Bit 1 = not in table error (NIT).

Bit 0 = unexpected K character error (UEK).

0x480

ECNT_CTRL0

[7:6]

RESERVED

Reserved.

0x0

[5:3]

ECNT_ENA0

Error counter enables for Lane 0. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane are

addressed as follows:

0x7

R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0]

ECNT_RST0

Reset error counters for Lane 0. This control

is paged by the LINK_PAGE control in

addressed as follows:

0x7

R/W

Bit 2 = bad disparity error (BDE).

Bit 1 = not in table error (NIT).

Bit 0 = unexpected K character error (UEK).

AD9175 Datasheet(PDF) 130 Page - Analog Devices

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