LXT975B datasheet(71/74 Pages) INTEL

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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975

Datasheet

19.3

Scrambler

Bypass

(100BASE-T

only)

1 = Bypass transmit scrambler and receive descrambler.

0 = Normal operation (scrambler and descrambler enabled).

R/W

Note 3

19.2

100BASE-FX

1 = Enable 100BASE fiber interface.

0 = Enable 100BASE twisted pair interface.

R/W

Note 4

19.1

Reserved

Write as 0; ignore on read.

R/W

19.0

Transmit

Disconnect

1 = Disconnect TP transmitter from line.

0 = Normal operation.

R/W

Table 55. Port Status Register (Address 20, Hex 14)

Bit

Name

Description

Type 1

Default

20.15:14

Reserved

Write as 0, ignore on read.

R/W

N/A

20.13

Link

1 = Link is up.

0 = Link is down.

Link bit 20.13 is a duplicate of bit 1.2, except that it is a dynamic

indication, whereas bit 1.2 latches Low.

20.12

Duplex

Mode

1 = Full-Duplex.

0 = Half-Duplex.

Note 2

20.11

Speed

1 = 100 Mbps operation.

0 = 10 Mbps operation.

Note 2

20.10

Reserved

Ignore.

RO/LH

N/A

20.9

Auto-Negotiation

Complete

1 = Auto-negotiation process complete.

0 = Auto-negotiation process not complete.

Auto-Negotiation Complete bit 20.9 is a duplicate of bit 1.5.

RO/LH

20.8

Page

Received

1 = Three identical and consecutive link code words received.

0 = Three identical and consecutive link code words not received.

Page Received bit 20.8 is a duplicate of bit 6.1.

RO/LH

20:7

Reserved

Write as 0, ignore on read.

R/W

20.6

Stream cipher

lock (100BASE-

TX only)

1 = Stream cipher locked.

0 = Stream cipher not locked.

20.5

Symbol Error

1 = Symbol error detected.

0 = No symbol error detected.

RO/

N/A

1. R/W = Read /Write

RO = Read Only

LH = Latching High

2. Bits 20.12 and 20.11 reflect the current operating mode of the LXT974/975.

Table 54. Port Configuration Register (Address 19, Hex 13) (Continued)

Bit

Name

Description

Type 1

Default

1. R/W = Read/Write

2. If auto-negotiation is disabled, the default value of bit 19.8 is determined by pin 115 (CFG_1). If CFG_1 is High, the default

value of

bit 19.8 = 1.

If CFG_1 is Low, the default value of bit 19.8 = 0. If auto-negotiation is enabled, the default value of bit 19.8 = 0.

3. The default value of bit 19.3 is determined by BYPSCR. If BYPSCR is High, the default value of bit 19.3 = 1.

If BYPSCR is Low, the default value of bit 19.3 = 0.

4. The default value of bit 19.2 is determined by the SD/TPn pin for the respective port.

If SD/TPn is tied Low, the default value of bit 19.2 = 0. If SD/TPn is not tied Low, the default value of bit 19.2 = 1.

On the LXT975, this bit is ignored on ports 0 and 2 that operate in twisted-pair mode only.

LXT975B Datasheet(PDF) 71 Page - Intel Corporation

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