LXT975B datasheet(17/74 Pages) INTEL

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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975

Datasheet

Table 9.

LXT974 and LXT975 Miscellaneous Signal Descriptions

Pin#

Symbol

Type1

Signal Description2

ADD4

ADD3

ADD2

Address <4:2>. Set upper three bits of PHY

address. ADD<1:0> are set internally to match

port number as shown at right.

ADD1

ADD0

Port

101, 112, 159

TEST

Test. Must be tied Low.

140

RBIAS

Bias. This pin provides bias current for the internal circuitry. Must be tied to

ground through a 22 k

Ω resistor.

118

CLK25M

Clock Input. A 25 MHz clock input is required at this pin. Refer to Functional

Description for detailed clock requirements.

109

RESET

Reset. This active Low input is OR’ed with the control register Reset bit (0.15).

The LXT974/975 reset cycle is extended 205

µs (nominal) after Reset is de-

asserted.

102

PWRDN

Power Down. When High, forces LXT974/975 into power down mode. This pin is

OR’ed with the Power Down bit (0.11). Refer to Table 44 on page 64 for more

information.

41, 119, 120

N/C

No Connection. Leave open.

1. Type Column Coding: I = Input, O = Output, A = Analog.

2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

Table 10. LXT974 and LXT975 LED Indicator Signal Descriptions

Pin#2

Symbol

Type1

Signal Description3

LED0_0

LED1_0

LED2_0

LED3_0

LED0 - Ports 0 - 3. In default mode, active Low output indicates transmitter active. However,

LED0 is programmable and may also be set to indicate receiver active, link status or duplex

status. Refer to LED Configuration Register, Table 51 on page 68, for details on

programming options.

LED0_1

LED1_1

LED2_1

LED3_1

LED1 - Ports 0 - 3. In default mode, active Low output indicates receiver active. However,

LED1 is programmable and may also be set to indicate link status, duplex status, or operating

speed. Refer to LED Configuration Register, Table 51 on page 68, for details on

programming options.

LED0_2

LED1_2

LED2_2

LED3_2

LED2 - Ports 0 - 3. In default mode, active Low output indicates link up. However, LED2 is

programmable and may also be set to indicate duplex status, operating speed or collision.

Refer to LED Configuration Register, Table 51 on page 68, for details on

programming options.

LEDENA

LED Enable. Active High output signals external device that LEDDAT is active.

LEDCLK

LED Clock. 25 MHz clock for LED serial data output.

LEDDAT

LED Data. Serial data output for 24 LEDs (6 x 4 ports) data.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain.

2. Unused pins should be tied Low.

3. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

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