LXT975B datasheet(14/74 Pages) INTEL

14 / 74 page

LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers

Datasheet

Table 7.

LXT974 and LXT975 MII Signal Descriptions

Pin#3

Symbol

Type1

Signal Description2

MII Data Interface Pins

TXD0_0

TXD0_1

TXD0_2

TXD0_3

Transmit Data - Port 0. Inputs containing NRZ data to be transmitted from port 0.

TXD1_0

TXD1_1

TXD1_2

TXD1_3

Transmit Data - Port 1. Inputs containing NRZ data to be transmitted from port 1.

TXD2_0

TXD2_1

TXD2_2

TXD2_3

Transmit Data - Port 2. Inputs containing NRZ data to be transmitted from port 2.

TXD3_0

TXD3_1

TXD3_2

TXD3_3

Transmit Data - Port 3. Inputs containing NRZ data to be transmitted from port 3.

TX_EN0

TX_EN1

TX_EN2

TX_EN3

Transmit Enable - Ports 0 - 3. Active High input enables respective port transmitter. This

signal must be synchronous to the TX_CLK.

TX_CLK0

TX_CLK1

TX_CLK2

TX_CLK3

Transmit Clock - Ports 0 - 3. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps

operation. The transmit data and control signals must always be synchronized to TX_CLK

by the MAC. The LXT974/975 normally samples these signals on the rising edge of

TX_CLK. However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1.

In this mode, the LXT974/975 samples the transmit data and control signals on the falling

edge of TX_CLK.

TX_ER0

TX_ER1

TX_ER2

TX_ER3

Transmit Coding Error - Ports 0 - 3. This signal must be driven synchronously to TX_CLK.

When High, forces the respective port to transmit Halt (H) code group.

RXD0_0

RXD0_1

RXD0_2

RXD0_3

Receive Data - Port 0. Receive data signals (4-bit parallel nibbles) are driven synchronously

to RX_CLK0.

RXD1_0

RXD1_1

RXD1_2

RXD1_3

Receive Data - Port 1. Receive data signals (4-bit parallel nibbles) are driven synchronously

to RX_CLK1.

RXD2_0

RXD2_1

RXD2_2

RXD2_3

Receive Data - Port 2. Receive data signals (4-bit parallel nibbles) are driven synchronously

to RX_CLK2.

RXD3_0

RXD3_1

RXD3_2

RXD3_3

Receive Data - Port 3. Receive data signals (4-bit parallel nibbles) are driven synchronously

to RX_CLK3.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain

2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

3. Unused pins should be tied Low.

LXT975B Datasheet(PDF) 14 Page - Intel Corporation

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