LXT975B datasheet(15/74 Pages) INTEL

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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975

Datasheet

RX_DV0

RX_DV1

RX_DV2

RX_DV3

Receive Data Valid - Ports 0 - 3. These signals are synchronous to the respective

RX_CLKn. Active High indication that received code group maps to valid data.

RX_ER0

RX_ER1

RX_ER2

RX_ER3

Receive Error - Ports 0 - 3. These signals are synchronous to the respective RX_CLKn.

Active High indicates that received code group is invalid, or that PLL is not locked.

RX_CLK0

RX_CLK1

RX_CLK2

RX_CLK3

Receive Clock - Ports 0 - 3. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.

COL0

COL1

COL2

COL3

Collision Detected - Ports 0 - 3. Active High outputs asserted upon detection of a collision.

Remain High for the duration of the collision. These signals are generated asynchronously.

Inactive during full-duplex operation.

CRS0

CRS1

CRS2

CRS3

Carrier Sense - Ports 0 - 3. Active High signals. During half-duplex operation

(bit 0.8 = 0), CRSn is asserted when either transmit or receive medium is non-idle. During

full-duplex operation (bit 0.8 = 1), CRSn is asserted only when the receive medium is non-

idle.

MII Control Interface Pins

MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel for PHY/STA

communication.

MDINT

Management Data Interrupt. An active Low output on this pin indicates status change.

Interrupt is cleared by sequentially reading Register 1, then Register 18.

MDC

Management Data Clock. Clock for the MDIO serial data channel.

Maximum frequency is 2.5 MHz.

100

MDDIS

Management Disable.

When MDDIS is High, the MDIO is restricted to Read Only and the Hardware Control

Interface pins provide continual control of their respective bits.

When MDDIS is Low at power up or Reset, the Hardware Control Interface pins control only

the initial or “default” values of their respective register bits. After the power-up/reset cycle is

complete, bit control reverts to the MDIO serial channel.

106

105

104

103

TRSTE0

TRSTE1

TRSTE2

TRSTE3

Tristate - Ports 0 - 3. This bit controls bit 0.10 (Isolate bit). When TRSTEn is High, the

respective port isolates itself from the MII Data Interface.

When MDDIS is High, TRSTE provides continuous control over bit 0.10.

When MDDIS is Low, TRSTE sets the initial (default) value of bit 0.10 at Reset and then bit

control reverts back to the MDIO interface.

Table 7.

LXT974 and LXT975 MII Signal Descriptions (Continued)

Pin#3

Symbol

Type1

Signal Description2

1. Type Column Coding: I = Input, O = Output, OD = Open Drain

2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

3. Unused pins should be tied Low.

LXT975B Datasheet(PDF) 15 Page - Intel Corporation

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