LXT975B datasheet(23/74 Pages) INTEL

23 / 74 page

Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975

Datasheet

Carrier Sense

Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received

from the line and in some modes when a packet is transmitted.

On transmit, CRS is asserted on a 10 Mbps or 100 Mbps half-duplex link. Carrier sense is not

generated on transmit when the link is operating in full-duplex mode.

Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:

• De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to

appear somewhat shorter to the MAC than it actually is on the wire.

• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-

duplex mode.

Operational Loopback

Operational loopback is provided for 10 Mbps half-duplex links when bit 19.11 = 0. Data

transmitted by the MAC is looped back on the receive side of the MII. Operational loopback is not

provided for 100 Mbps links, full-duplex links, or when 19.11 = 1.

Test Loopback

A test loopback function is provided for diagnostic testing of the LXT974/LXT975. During test

loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally

looped back by the LXT974/975 and returned to the MAC.

Test loopback is available for 100TX, 100FX, and 10T operation. Test loopback is enabled by

setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). The

desired mode of operation for test loopback is set using bits 0.13 and 19.2 as shown in Table 13.

Loopback paths for the three modes of operation are shown in Figure 7.

Table 13. Test Loopback Operation

Mode of Operation

Bit

19.2

0.13

10T Test Loopback

100TX Test Loopback

100FX Test Loopback

1. Bit 0.14 = 1, bit 0.8 = 1, and 0.12 = 0 must also be set to enable Test Loopback.

LXT975B Datasheet(PDF) 23 Page - Intel Corporation