SAM5708B datasheet(85/89 Pages) ETC1

85 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

12.

Recommended Board Layout

Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for

reliable operations:

12.1. GND, VD33, VM, VC12, VD12 distribution, decoupling

All GND, VD33, VM, VC12, VD12 pins should be connected. A GND plane is strongly

recommended. The board GND, VD33, VM and VC12, VD12 distribution should be in grid form.

Recommended VD12 decoupling is 100nF+10nF at each VD12 pin of the IC with additional 10µFT

on two opposite sides

VC12 requires 10µFT +100nF on each pin.

Minimum recommended VM decoupling is 0.1µF at half of VM pins. 10nF should be connected at

the other half of VM pins. 10µFT should be also added on two opposite sides.

Recommended VD33 decoupling is 0.1µF at each VD33 pin.

VD33R requires a single 10µFT decoupling.

VD330 requires a single 100nF decoupling.

VD33U requires 10µFT+100nF+10nF capacitors.

12.2. Crystal

The paths between the crystal, the crystal compensation capacitors and the IC should be short

and shielded. The ground return from the compensation capacitors filter should be the GND plane

from the IC.

12.3. Busses

Parallel layout from D15-D0 and MA26-MA0/MD15-MD0 should be avoided. The D15-D0 bus is an

asynchronous type bus. Even on short distances, it can induce pulses on MA26-MA0/MD15-MD0

which can corrupt address and/or data on these busses.

A ground plane should be implemented below the D16-D0 bus, which connects both to the host

and to SAM5708B GND.

A ground plane should be implemented below the MA26-MA0/MD15-MD0 bus, which connects

both to the NOR Flash grounds and to SAM5708B.

A ground plane should be implemented below the MA18-MA0/MD15-MD0 bus, which connects

both to the SRAM grounds and to SAM5708B.

A ground plane should be implemented below the NDIO8-NDIO0 bus, which connects both to the

NAND Flash grounds and to SAM5708B.

SAM5708B Datasheet(PDF) 85 Page - List of Unclassifed Manufacturers