SAM5708B datasheet(5/89 Pages) ETC1

5 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

1.5.

Async Busses

As shown in the general block diagram, several 24-bit Async Busses can be accessed by most of

masters (P16XT, P24XT,

DMA controller,…) in a parallel way. Two busses XBUS0 & XBUS1 give

access to external memories.

1.6.

Enhanced 16-bit CPU

– P16XT

The SAM5708B operates under the control of a new highly speed optimized 16-bit CPU (P16XT).

The key features of the P16XT are the following:

 Operating frequency = 196.6 MHz

 New instructions including 32 bit data handling and 32x32 multiply

 Maximum executable program size = 512k words

 Backward compatibility with previous P16 products and optimized instruction set for C-

compiler

 Interrupt handling: 3 interrupt signals, 32 sources with programmable Mask, Polarity &

Triggering mode

A tightly coupled code/cache memory allows the P16XT to fetch code lines with reduced latency

when needed. This memory can be either used as code memory when the whole firmware can be

stored in internal memory or as cache memory (n-Way Set Associative Cache System) in other

cases. The internal code/cache memory is loaded during the boot sequence (at power-up) by

P16XT ROM boot program.

By default, the code/cache memory has a size of 512kbits (32k*16). Depending on performance

requirements, the distribution of internal memory between code/cache and data/effect partitions

can be modified as explained in the next paragraph.

The P16XT ROM holds the boot program as well as a debugger which uses a dedicated

asynchronous serial line.

SAM5708B Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers