SAM5708B datasheet(65/89 Pages) ETC1

65 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

Host write should be done with following steps:

a) Read status (A0=1). If bit RF=0, go to step b). If bit RF=1, read again status till bit RF going to 0.

b) Write new data (A0=0) or new control (A0=1)

Note about step a):

There are two different cases for RF bit being 1:

- RF bit is 1 because FIFO of P16 is full. RF bit will go low again as soon as P16 is reading some

bytes of the FIFO in order to have some free space again inside fifo and then is clearing bit 7

(FIFULL) of port 1 (CONTROL/STATUS). This time is firmware dependant.

- RF bit is 1 because previous host write has still not been written into the P16 FIFO. This case can

happen if P16 is executing a long instruction. The writing will be indeed performed only when P16

has finished the instruction.

8.8.2. Host Parallel Interface mode 1 (fast data transfer)

Pins used in mode 1 (A1=1):

D7-D0 or D15-D0 (I/O)

CS/ (input)

A1-

A0 (input): Addresses from host (input), A1=1 to select mode 1, A0 is “don’t care”.

WR/ (input)

RD/ (input)

XFR_RDY (output)

This interface is used for fast read/write transfer between host processor and SAM5708B. Typical

applications are direct fast sound bank transfer from host to SDRAM and streaming audio.

However, any other devices connected to internal async bus of SAM5708B can be also accessed

by host through this interface (other external memories, internal ram, router and P24 memories,

etc…). Single or burst read/write modes are available. Read/write mode is selected by firmware

8.8.2.1.

HPI mode 1, Read Timing

tcslrdl

CS/

RD/

A[1:0]

D[15:0]

XFR_RDY

tprd

trdhcsh

tavdv

tarh

trdldv

tdrh

trdhdrl

tpdrrd

XFR 16-bit, single read cycle

tavrdh

tdvrdh

tdah

SAM5708B Datasheet(PDF) 65 Page - List of Unclassifed Manufacturers

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