SAM5708B datasheet(57/89 Pages) ETC1

57 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

8.4.

NAND Flash interface

8.4.1. Overview

SAM5708B can access to NAND Flash device in two ways:

 Direct communication through the NAND Flash controller. Used by P16 for NAND bad block

management

 Communication through a built-in NAND Flash sequencer that will take care of transfers from

the NAND Flash device to the external RAM buffer by automatically writing in NAND Flash

controller registers. Used by sample cache module to feed P24 requests.

NAND Flash controller has following features:

 Handles automatic Read/write transfer through 2x2112 byte SRAM buffer

 DMA support

 Support SLC NAND Flash technology

 Programmable timing on SysClk basis

 Programmable Flash Data width 8-bit or 16-bit

 Automatic error correction while reading or writing with 4D-Hamming (up to 9 bit errors

correction)

 Support Enhanced Data Output (EDO)

Pins used:

NDIO7-0: I/O for Address, Data and Command transfer on 8-bit width.

NDCE0/, NDCE1/: Chip Enable

NDALE: Address Latch Enable.

NDCLE: Command Latch Enable

NDWE/: Write Enable

NDRE/: Read Enable

NDR|B/: Ready Busy status

8.4.2. NAND Flash features

The NAND flash devices that can be used with SAM5708B need to have the following features:

SLC technology

ONFI compliant

Read Cache Random (00h/31h) and Read Cache End commands support (3Fh)

2kByte or 4kByte page size

in case of multi-plane organization, it must support interleave (multi-plane)

operations and must have the 'No block address restrictions' set inside its

interleaved operation attributes

spare area at least 64 Bytes (for hamming ECC) by 2kBytes area

page per block: 64,128, 256 or 512

5 address cycles max

8 GByte size max

8-bit bus width

SAM5708B Datasheet(PDF) 57 Page - List of Unclassifed Manufacturers

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