SAM5708B datasheet(71/89 Pages) ETC1

71 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

8.9.

Serial Slave Asynchronous Interface (UART / MIDI)

The SAM5708B can be controlled by an external host processor through this bidirectional serial

interface.

Pins used:

MIDI_IN1, MIDI_OUT1: UART / MIDI port 1

MIDI_IN2, MIDI_OUT2: UART / MIDI port 2

The serial signals on MIDI_IN and MIDI_OUT pins are asynchronous signals following the UART /

MIDI transmission standard:

Baud rate: programmable up to >400kb/s, typically 31.25 kb/s (MIDI) or 38.4kb/s (COM)

Format: start bit (0), 8 data bits, stop bit (1)

8.10. Serial Slave Synchronous Interface

The SAM5708B can be controlled by an external host processor through this unidirectional serial

interface.

Pins used:

SSCLK, SSYNC, SSDIN (input)

SSINT/ (output)

Data is shifted MSB first. SAM5708B samples an incoming SSDIN bit on the rising edge of

SSCLK, therefore the host should change SSDIN on the negative SCLK edge.

SSYNC allows initial synchronization. The rising edge of SSYNC, which should occur with SSCLK

low, indicates that SSDIN will hold MSB data on the next rising SSCLK.

The data is stored internally into a FIFO. Size of FIFO is firmware dependent. Minimum size is 128

bytes. Host should stop sending data as soon as SSINT/ goes high.

When the FIFO count is below 64, the SSINT/ output goes low. This allows the host processor to

send data in burst mode.

The maximum SSCLK frequency is fsck/4 (fsck being the system clock frequency. fsck =1/spck).

The minimum time between two bytes is 256 spck.

The contents of the SSDIN data are defined by the firmware.

MSB

SCLK

SDIN

Serial Slave Interface typical timing

SYNC

SAM5708B Datasheet(PDF) 71 Page - List of Unclassifed Manufacturers