SAM5708B datasheet(83/89 Pages) ETC1

83 / 89 page

SAM5708B

SAM5708B.pdf

– Rev 14/05/2018

11.

Reset and Power Down

During power-up, the RST/ input should be held low until the core is stabilized in reset state, which

takes 10ms Max.

After the low to high transition of RST/, following happens:

- Oscillator OSC1 is started

- P16 program execution starts in built-in ROM

- PLL is started and stabilized after 2.5 ms typ

- P16 application program loading starts.

If RST/ is asserted low then the crystal oscillators and PLLs will be stopped.

Other power reduction features allowing warm restart are controlled by firmware:



P24s can be individually stopped



The clock frequency can be internally divided by 256



ADC can be disabled



Controllers for USB, Ethernet or SDRAM can be individually switched off

11.1. Power-up sequence

At power-up the following sequence is executed:

1. STIN is sensed. If HIGH, then the built-in debugger is started.

2. If MC2-0 bits were preprogrammed they are read from eFuse. Otherwise MC2-0 pins are

sensed and corresponding Memory Config is set

3. ROM boot tries to identify source for firmware.

For that it tries to find “DR” marker for Dream

firmware. This step is done in slow mode (PLL not started). During this step, rom boot set the

minimum of primary functions to avoid any potential conflict of some pins. Accesses to

memories are done with longest access time, most simple protocol (accessing for example

Quad SPI memory in single mode rather than quad mode). ROM boot searches source in

following order:

a) Main Memory. According to Memory Config, Main Memory can be: NOR Flash, NAND

Flash, Quad Nor Flash

b) Multi-Purpose Quad SPI

4. If valid firmware has not been found, firmware download from a host processor is assumed into

internal RAM (56k x16 max) via Host Parallel Interface.

a) The byte 0ACh is written to the host. The host checks status and can recognize that the

chip is ready to accept program download.

b) The host sends the Boot_Info table (low byte first, 20 * 2 bytes). Boot_Info table contains

info on firmware size, primary and secondary functions setting, memory and software

config. The Boot_Info table is generated by SamVS , and is located in the firmware binary

file at word addresses 1-20.

c) SAM5708B sends ACh when initializations are ready

d) The host sends the SAM5708B firmware binary from word address 400h, 2*DownLoadSize

bytes, low byte first.

"DownLoadSize" is defined in the Boot_Info table at word address 3.

e) The byte 0ACh is written to the host. The host checks status and can recognize that the

chip has accepted the firmware.

SAM5708B starts the firmware.

Note: Be aware that at boot time the IRQ signal is not used, the Host CPU must read the port

status register (TE/RF bits) before sending or reading a data byte to/from SAM5708B via 8-bit

parallel port.

SAM5708B Datasheet(PDF) 83 Page - List of Unclassifed Manufacturers

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