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C161 Datasheet(PDF) 265 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 265 Page - Infineon Technologies AG |
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265 / 400 page  &3, 7KH :DWFKGRJ 7LPHU :'7 User’s Manual 13-3 1999-08 13.1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload value for the high byte of the timer, selects the input clock prescaling factor and also provides flags that indicate the source of a reset. After any reset (except see note) the watchdog timer is enabled and starts counting up from 0000 H with the default frequency fWDT = fCPU/2. The default input frequency may be changed to another frequency ( f WDT = fCPU/128) by programming the prescaler (bit WDTIN). The watchdog timer can be disabled by executing the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT (End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions disables the execution of DISWDT. Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled. The software reset that terminates the BSL mode will then enable the WDT. When the watchdog timer is not disabled via instruction DISWDT it will continue counting up, even during Idle Mode. If it is not serviced via the instruction SRVWDT by the time the count reaches FFFF H the watchdog timer will overflow and cause an internal reset. This reset will pull the external reset indication pin RSTOUT low. The Watchdog Timer Reset Indication Flag (WDTR) in register WDTCON will be set in this case. In bidirectional reset mode also pin RSTIN will be pulled low for the duration of the internal reset sequence and a long hardware reset will be indicated instead. A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active (low) after the programmed waitstates. Otherwise the external bus cycle will be aborted. To prevent the watchdog timer from overflowing it must be serviced periodically by the user software. The watchdog timer is serviced with the instruction SRVWDT which is a protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON. Servicing the watchdog timer will also reset bit WDTR. After being serviced the watchdog timer continues counting up from the value (<WDTREL> * 2 8). |
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