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C161 Datasheet(PDF) 222 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 222 Page - Infineon Technologies AG |
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222 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-30 1999-08 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to ‘001 B’. In counter mode timer T5 can be clocked by a transition of timer T6’s output toggle latch T6OTL (i.e. timer concatenation). The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at the toggle latch T6OTL. Bit field T5I in control register T5CON selects the triggering transition (see table below). Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5. Table 10-8 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection T5I Triggering Edge for Counter Increment / Decrement X 0 0 None. Counter T5 is disabled 0 0 1 Reserved. Do not use this combination. 0 1 0 Reserved. Do not use this combination. 0 1 1 Reserved. Do not use this combination. 1 0 1 Positive transition (rising edge) of output toggle latch T6OTL 1 1 0 Negative transition (falling edge) of output toggle latch T6OTL 1 1 1 Any transition (rising or falling edge) of output toggle latch T6OTL |
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