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C161 Datasheet(PDF) 219 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 219 Page - Infineon Technologies AG |
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219 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-27 1999-08 Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to ‘000 B’. In this mode, T6 is clocked with the internal system clock divided by a programmable prescaler, which is selected by bit field T6I. The input frequency f T6 for timer T6 and its resolution r T6 are scaled linearly with lower clock frequencies fCPU, as can be seen from the following formula: Figure 10-17 Block Diagram of Core Timer T6 in Timer Mode The timer input frequencies, resolution and periods which result from the selected prescaler option are listed in the table below. This table also applies to the auxiliary timer T5 in timer mode. Note that some numbers may be rounded to 3 significant digits. Note: Bitfield T6M in register T6CON will be ‘000 B’ after reset. Do not modify this bitfield to any other value. Table 10-7 GPT2 Timer Input Frequencies, Resolution and Periods f CPU = 20MHz Timer Input Selection T5I / T6I 000 B 001 B 010 B 011 B 100 B 101 B 110 B 111 B Prescaler factor 4 8 16 32 64 128 256 512 Input Frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.06 kHz Resolution 200ns 400 ns 800 ns 1.6 µs3.2 µs6.4 µs12.8 µs 25.6 µs Period 13 ms 26 ms 52.5 ms 105 ms 210 ms 420 ms 840 ms 1.68 s f T6 = f CPU 4 * 2 <T6I> r T6 [µs] = f CPU [MHz] 4 * 2 <T6I> Core Timer Tx TxOTL Interrupt Request TxR 2n : 1 Txl MCB02028C.VSD f CPU Up/ Down |
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