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C161 Datasheet(PDF) 217 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 217 Page - Infineon Technologies AG |
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217 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-25 1999-08 10.2.1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register T6CON. T6CON Timer 6 Control Register SFR (FF48 H/A4H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 SR --- - T6 OTL -- T6 UD T6R T6M T6I rw - - - - rwh - - rw rw rw rw Bit Function T6I Timer 6 Input Selection Depends on the Operating Mode, see respective sections. T6M Timer 6 Mode Control (Basic Operating Mode) 000: Timer Mode 001: Reserved. Do not use this combination. 010: Reserved. Do not use this combination. 011: Reserved. Do not use this combination. 1XX: Reserved. Do not use this combination. T6R Timer 6 Run Bit 0: Timer / Counter 6 stops 1: Timer / Counter 6 runs T6UD Timer 6 Up / Down Control 0: Timer / Counter 6 counts up 1: Timer / Counter 6 counts down T6OTL Timer 6 Output Toggle Latch Toggles on each overflow / underflow of T6. Can be set or reset by software. T6SR Timer 6 Reload Mode Enable 0: Reload from register CAPREL Disabled 1: Reload from register CAPREL Enabled |
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