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C161 Datasheet(PDF) 215 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 215 Page - Infineon Technologies AG |
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215 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-23 1999-08 10.2 Timer Block GPT2 From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded. Figure 10-15 SFRs and Port Pins Associated with Timer Block GPT2 Timer block GPT2 supports high precision event control with a maximum resolution of 8 TCL. It includes the two timers T5 and T6, and the 16-bit capture/reload register CAPREL. Timer T6 is referred to as the core timer, and T5 is referred to as the auxiliary timer of GPT2. The count direction (Up / Down) may be programmed via software. An overflow/ underflow of T6 is indicated by the output toggle bit T6OTL. In addition, T6 may be reloaded with the contents of CAPREL. The toggle bit also supports the concatenation of T6 with auxiliary timer T5. Triggered by an external signal, the contents of T5 can be captured into register CAPREL, and T5 may optionally be cleared. Both timer T6 and T5 can count up or down, and the current timer value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6. ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register T5CON GPT2 Timer 5 Control Register T6CON GPT2 Timer 6 Control Register CAPIN/P3.2 T5CON Control Registers T5 GPT2 Timer 5 Register T6 GPT2 Timer 6 Register CAPREL GPT2 Capture/Reload Register T5IC GPT2 Timer 5 Interrupt Control Register T6IC GPT2 Timer 6 Interrupt Control Register CRIC GPT2 CAPREL Interrupt Control Register Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control T5 T5IC DP3 P3 T6 CAPREL T6IC CRIC T6CON ODP3E |
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