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C161 Datasheet(PDF) 220 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 220 Page - Infineon Technologies AG |
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220 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-28 1999-08 10.2.2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer mode with the same options for the timer frequencies as the core timer T6. In addition the auxiliary timer can be concatenated with the core timer (operation in counter mode). Its contents may be captured to register CAPREL upon a selectable trigger. The individual configuration for timer T5 is determined by its bitaddressable control register T5CON. Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers. Note: The auxiliary timer has no output toggle latch and no alternate output function. T5CON Timer 5 Control Register SFR (FF46 H/A3H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5 SC T5 CLR CI - CT3 - T5 UDE T5 UD T5R T5M T5I rw rw rw - rw - rw rw rw rw rw Bit Function T5I Timer 5 Input Selection Depends on the Operating Mode, see respective sections. T5M Timer 5 Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 01x: Reserved. Do not use this combination. 1xx: Reserved. Do not use this combination. T5R Timer 5 Run Bit 0: Timer / Counter 5 stops 1: Timer / Counter 5 runs T5UD Timer 5 Up / Down Control 0: Timer / Counter 5 counts up 1: Timer / Counter 5 counts down CT3 Timer 3 Capture Trigger Enable 0: Capture trigger from pin CAPIN 1: Capture trigger from T3 input pins |
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