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C161 Datasheet(PDF) 230 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 230 Page - Infineon Technologies AG |
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230 / 400 page  &3, 7KH $V\QFKURQRXV6\QFKURQRXV 6HULDO ,QWHUIDFH User’s Manual 11-2 1999-08 The operating mode of the serial channel ASC0 is controlled by its bitaddressable control register S0CON. This register contains control bits for mode and error check selection, and status flags for error identification. S0CON ASC0 Control Register SFR (FFB0 H/D8H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S0R S0 LB S0 BRS S0 ODD - S0 OE S0 FE S0 PE S0 OEN S0 FEN PEN S0 REN S0 STP S0M rw rw rw rw - rwh rwh rwh rw rw rw rwh rw rw Bit Function S0M ASC0 Mode Control 000: 8-bit data synchronous operation 001: 8-bit data async. operation 010: Reserved. Do not use this combination! 011: 7-bit data + parity async. operation 100: 9-bit data async. operation 101: 8-bit data + wake up bit async. operation 110: Reserved. Do not use this combination! 111: 8-bit data + parity async. operation S0STP Number of Stop Bits Selection async. operation 0: One stop bit 1: Two stop bits S0REN Receiver Enable Bit 0: Receiver disabled 1: Receiver enabled (Reset by hardware after reception of byte in synchronous mode) S0PEN Parity Check Enable Bit async. operation 0: Ignore parity 1: Check parity S0FEN Framing Check Enable Bit async. operation 0: Ignore framing errors 1: Check framing errors S0OEN Overrun Check Enable Bit 0: Ignore overrun errors 1: Check overrun errors S0PE Parity Error Flag Set by hardware on a parity error (S0PEN=’1’). Must be reset by software. |
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