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C161 Datasheet(PDF) 233 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 233 Page - Infineon Technologies AG |
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233 / 400 page ![]() &3, 7KH $V\QFKURQRXV6\QFKURQRXV 6HULDO ,QWHUIDFH User’s Manual 11-5 1999-08 11.1 Asynchronous Operation Asynchronous mode supports full-duplex communication, where both transmitter and receiver use the same data frame format and the same baud rate. Data is transmitted on pin TXD0 and received on pin RXD0. These signals are alternate port functions. Asynchronous Data Frames 8-bit data frames either consist of 8 data bits D7...D0 (S0M=’001 B’), or of 7 data bits D6...D0 plus an automatically generated parity bit (S0M=’011 B’). Parity may be odd or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the 7 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.7. Figure 11-2 Asynchronous Mode of Serial Channel ASC0 |
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