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C161 Datasheet(PDF) 231 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 231 Page - Infineon Technologies AG |
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231 / 400 page  &3, 7KH $V\QFKURQRXV6\QFKURQRXV 6HULDO ,QWHUIDFH User’s Manual 11-3 1999-08 A transmission is started by writing to the Transmit Buffer register S0TBUF (via an instruction or a PEC data transfer). Only the number of data bits which is determined by the selected operating mode will actually be transmitted, i.e. bits written to positions 9 through 15 of register S0TBUF are always insignificant. After a transmission has been completed, the transmit buffer register is cleared to 0000 H. Data transmission is double-buffered, so a new character may be written to the transmit buffer register, before the transmission of the previous character is complete. This allows the transmission of characters back-to-back without gaps. Data reception is enabled by the Receiver Enable Bit S0REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) Receive Buffer register S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected operating mode will be read as zeros. Data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. In all modes, receive buffer overrun error detection can be selected through bit S0OEN. When enabled, the overrun error status flag S0OE and the error interrupt request flag S0EIR will be set when the receive buffer register has not been read by the time reception of a second character is complete. The previously received character in the receive buffer is overwritten. S0FE Framing Error Flag Set by hardware on a framing error (S0FEN=’1’). Must be reset by software. S0OE Overrun Error Flag Set by hardware on an overrun error (S0OEN=’1’). Must be reset by software. S0ODD Parity Selection Bit 0: Even parity (parity bit set on odd number of ‘1’s in data) 1: Odd parity (parity bit set on even number of ‘1’s in data) S0BRS Baudrate Selection Bit 0: Divide clock by reload-value + constant (depending on mode) 1: Additionally reduce serial clock to 2/3rd S0LB LoopBack Mode Enable Bit 0: Standard transmit/receive mode 1: Loopback mode enabled S0R Baudrate Generator Run Bit 0: Baudrate generator disabled (ASC0 inactive) 1: Baudrate generator enabled Bit Function |
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