XRT79L71IB datasheet(23/441 Pages) EXAR

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PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

B11

TxOHFrame/

TxHDLCClk

Transmit Overhead Framing Pulse/Transmit HDLC Controller Clock Output

pin:

The function of this output pin depends upon whether or not the XRT79L71 has

been configured to operate in the High-Speed HDLC Controller Mode.

Non-High-Speed HDLC Controller Mode - TxOHFrame:

This output pin pulses high for one TxOHClk period coincident with the instant

the Transmit Overhead Data Input Interface would be accepting the first over-

head bit within an outbound DS3 or E3 frame.

High Speed HDLC Controller Mode - TxHDLCClk:

This output pin functions as the demand clock output signal for the Transmit

HDLC Controller byte-wide input interface. This clock signal is ultimately derived

from either the TxInClk or the RxOutClk signal. Hence, the frequency of this

clock signal is nominally one-eight of that of the TxInClk or the RxOutClk signals.

The Transmit HDLC Controller block will sample the contents of the Transmit

HDLC Controller byte-wide input interface, upon the rising edge of this clock out-

put signal. Therefore, the local terminal equipment should be designed to output

data onto the TxHDLCDat[7:0] bus upon the falling edge of this clock output sig-

nal.

A12

TxOHEnable/

TxHDLCDat_7

I/O

Transmit Overhead Enable Output indicator/Transmit HDLC Controller Data

Bit 7 Input:

The function of this input pin depends upon whether or not the XRT79L71 is con-

figured to operate in the High Speed HDLC Controller Mode.

Non-High Speed HDLC Controller Mode - TxOHEnable:

The XRT79L71 will assert this output pin, for one TxInClk period, just prior to the

instant that the Transmit Overhead Data Input Interface will be sampling and pro-

cessing an overhead bit.

If the local terminal equipment intends to insert its own value for an overhead bit,

into the outbound DS3 or E3 data stream, then it is expected to sample the state

of this signal, upon the falling edge of TxInClk. Upon sampling the TxOHEnable

signal "High", the local terminal equipment should;

(1) place the desired value of the overhead bit onto the TxOH input pin and

(2) assert the TxOHIns input pin.

The Transmit Overhead Data Input Interface block will sample and latch the data

on the TxOH signal, upon the rising edge of the very next TxInClk input signal.

High-Speed HDLC Controller Mode - TxHDLCDat_7:

If the XRT79L71 is configured to operate in the High-Speed HDLC Controller

mode, then the local terminal equipment will be provided with a byte-wide Trans-

mit HDLC Controller byte-wide input interface. This input pin will function as Bit 7

(the MSB) within this byte wide interface.

Data, residing on the Transmit HDLC Controller byte wide input interface, will be

sampled upon the rising edge of the TxHDLCClk output signal.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 23 Page - Exar Corporation

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