XRT79L71IB datasheet(45/441 Pages) EXAR

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PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

RxUPrty/

RxPPrty

Receive UTOPIA Interface - Parity Output pin/Receive POS-PHY Interface -

Parity Output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or the PPP Modes.

ATM UNI Mode - RxUPrty:

The Receive UTOPIA interface block will compute the odd-parity value of each

byte (or word) that it will place in the Receive UTOPIA Data Bus. This odd-par-

ity value will be output on this pin, while the corresponding byte (or word) is

present on the Receive UTOPIA Data Bus

PPP Mode - RxPPrty:

The Receive POS-PHY Interface block will compute the odd-parity value of

each byte (or word) that it will place in the Receive POS-PHY Data Bus. This

odd parity value will be output on this pin, which the corresponding byte (or

word) is present on the Receive POS-PHY Data Bus.

RxPEOP

Receive POS-PHY Interface - End of Packet:

The XRT79L71 drives this output pin "High" whenever the last byte of a given

Packet is being output via the RxPData[15:0] data bus.

NOTES:

This output pin is only valid when the XRT79L71 is configured to

operate in the PPP Mode.

This output pin is only valid when the Receive POS-PHY Interface -

Read Enable Output pin.

RxPDVAL

Receive POS-PHY Interface Signal Valid Indicator:

This output signal indicates whether or not the Receive POS-PHY Interface sig-

nals (e.g., PRData[15:0], RxPSOP, RxPEOP, RxPPrty, RxPERR) are valid.

This output pin will be driven "High", when these signals are valid. Conversely,

this output pin will be driven "Low" when these signals are NOT valid.

NOTE: This output pin is only active if the XRT79L71 has been configured to

operate in the PPP Mode.

RxAddr_0

RxAddr_1

RxAddr_2

RxAddr_3

RxAddr_4

Receive UTOPIA Address Bus input MSB:

These input pins functions as the Receive UTOPIA Address bus inputs. These

input pins are only active when the Framer/UNI device is operating in the ATM

UNI Mode. The Receive UTOPIA Address Bus input is sampled on the rising

edge of the RxClk signal. The contents of this address bus are compared with

the value stored in the Rx UT Address Register (Address = 0x6C). If these two

values match, then the UNI will inform the ATM Layer Processor on whether or

not it has any new ATM cells to be read from the RxFIFO by driving the RxClav

output to the appropriate level. If these two address values do not match, then

the UNI will not respond to the ATM Layer Processor and will keep its RxClav

output signal tri-stated.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 45 Page - Exar Corporation

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