XRT79L71IB datasheet(35/441 Pages) EXAR

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PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

PIN #NAME

TYPE

DESCRIPTION

RECEIVE SYSTEM SIDE INTERFACE PINS

RxAIS/

RxNib_2/

RxHDLCDat_2

Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/

Receive HDLC Controller Data Bus - Bit 2 output pin:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer/Nibble-Parallel Interface

Mode, the High-Speed HDLC Controller Mode, or in the other modes.

Other Modes - RxAIS:

This output pin is driven "High" whenever the Receive Section of the XRT79L71

has detected and is currently declaring an AIS (Alarm Indicator Signal) condi-

tion.

Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2:

If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this

output pin will function as the bit 2 output from the Receive Nibble-Parallel out-

put interface. The Receive Payload Data Output Interface block will output this

signal (along with RxNib_0, RxNib_1, and RxNib_3) upon the rising edge of the

RxClk output signal.

High-Speed HDLC Controller Mode - RxHDLCDat_2:

This output pin along with RxHDLCDat_[7:3] and RxHDLCDat_[1:0] functions

as the Receive HDLC Controller byte wide output data bus. The Receive HDLC

Controller will output the contents of all HDLC frames via this output data bus,

upon the rising edge of the RxHDLCClk output signal. Hence, the user's local

terminal equipment should be designed/configured to sample this data upon the

falling edge of the RxHDLCClk output clock signal.

RxRED/

RxNib_3/

RxHDLCDat_3

Receive Section Red Alarm Indicator/Receive Nibble Interface Output pin -

Bit 3/Receive HDLC Controller Data Bus output pin - Bit 3:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode, the

High-Speed HDLC Controller Mode, or in some other mode.

Clear-Channel Framer/Nibble-Parallel Mode - RxNib_3:

The XRT79L71 will output Received data from the remote terminal equipment

to the local terminal equipment via this pin, along with RxNib_0 through

RxNib_2. This particular output pin functions as the LSB. The data at this pin is

updated on the rising edge of the RxClk output signal. Hence, the user's local

terminal equipment should sample this signal upon the falling edge of RxClk.

High-Speed HDLC Controller Mode - RxHDLCDat_3:

This output pin along with RxHDLCDat_[7:4] and RxHDLCDat_[2:0] functions

as the Receive HDLC Controller byte wide output data bus. The Receive HDLC

Controller will output the contents of all HDLC frames via this output data bus,

upon the rising edge of the RxHDLCClk output signal. Hence, the user's local

terminal equipment should be designed/configured to sample this data upon the

falling edge of the RxHDLCClk output clock signal.

Other Modes - RxRED:

The Framer/UNI asserts this output pin to denote that one of the following

events has been detected by the Receive DS3/E3 Framer block:

• LOS - Loss of Signal Condition

• OOF - Out of Frame Condition

• AIS - Alarm Indication Signal Detection

XRT79L71IB Datasheet(PDF) 35 Page - Exar Corporation

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