XRT79L71IB datasheet(62/441 Pages) EXAR

62 / 441 page

XRT79L71

PRELIMINARY

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REV. P1.0.3

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

TRANSMIT PAYLOAD DATA INPUT INTERFACE

TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS

t11

TxUClav signal valid (not Hi-Z) from first TxUClk rising edge of

valid and correct TxUAddr[4:0]

3.6

9.7

t12

TxUClav signal Hi-Z from first TxUClk rising edge of different

TxUAddr[4:0]

3.6

9.7

TABLE 11: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK

Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified

SYMBOL

PARAMETER

MIN.TYP.MAX.UNITS

CONDITIONS

Transmit Payload Data Input Interface - Loop-Timed/Serial Mode (See Figure 13)

Payload data (TxSer) set-up time to rising edge of

RxOutClk

Payload data (TxSer) hold time, from rising edge of

RxOutClk

0ns

RxOutClk to TxFrame output delay

RxOutClk to TxOHInd output delay

Transmit Payload Data Input Interface - Local Timed/Serial Mode (See Figure 14)

Payload data (TxSer) set-up time to rising edge of

TxInClk

4ns

Payload data (TxSer) hold time, from rising edge of

TxInClk

0ns

TxFrameRef set-up time to rising edge of TxInClk

Framer IC is

Frame Slave

TxFrameRef hold-time, from rising edge of TxInClk

Frame IC is

Frame Slave

TxInClk to TxOHInd output delay

t10

TxInClk to TxFrame output delay

Transmit Payload Data Input Interface - Looped-Timed/Nibble Mode (See Figure 15)

t11

TxNib set-up time to third rising edge of RxOutClk

t12

Payload Nibble hold time, from latching edge of

RxOutClk

t13

TxNibClk to TxNibFrame output delay

DS3 Applications

E3 Applications

t13A

Max Delay of Rising Edge of TxNibClk to Data Valid

on TxNib[3:0]

DS3 Applications

E3 Applications

Transmit Payload Data Input Interface - Local-Timed/Nibble Mode (See Figure 16

TABLE 10: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK

SYMBOL

PARAMETER

MIN.TYP

MAX.UNITS

XRT79L71IB Datasheet(PDF) 62 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 62 Page - Exar Corporation

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