XRT79L71IB datasheet(38/441 Pages) EXAR

38 / 441 page

XRT79L71

PRELIMINARY

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REV. P1.0.3

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

RxOHEnable/

RxHDLCDat_5

Receive Overhead Data Output Interface - Enable Output/Receive HDLC

Controller Data Bus - Bit 5 output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer Mode or in the High-Speed

HDLC Controller Mode.

Clear-Channel Framer Mode - RxOHEnable:

The XRT79L71 will assert this output signal for one RxOHClk period when it is

safe for the local terminal equipment to sample the data on the RxOH output

pin.

High-Speed HDLC Controller Mode - RxHDLCDat_5:

This output pin along with RxHDLCDat_[4:0], RxHDLCDat_6 and

RxHDLCDat_7 functions as the Receive HDLC Controller byte wide output data

bus. The Receive HDLC Controller will output the contents of all HDLC frames

via this output data bus, upon the rising edge of the RxHDLCClk output signal.

Hence, the user's local terminal equipment should be designed/configured to

sample this data upon the falling edge of the RxHDLCClk output clock signal.

RxOH/

RxHDLCDat_6

Receive Overhead Data Output Interface - output/Receive HDLC Controller

Data Bus - Bit 6 output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer mode or in the High-Speed

HDLC Controller Mode.

Clear-Channel Framer Mode - RxOH:

All overhead bits, which are received via the Receive Section of the XRT79L71

will be output via this output pin, upon the rising edge of RxOHClk.

High-Speed HDLC Controller Mode - RxHDLCDat_6:

This output pin along with RxHDLCDat_[5:0] and RxHDLCDat_7 functions as

the Receive HDLC Controller byte wide output data bus. The Receive HDLC

Controller will output the contents of all HDLC frames via this output data bus,

upon the rising edge of the RxHDLCClk output signal. Hence, the user's local

terminal equipment should be designed/configured to sample this data upon the

falling edge of the RxHDLCClk output clock signal.

RxOHClk/

RxHDLCClk

Receive Overhead Data Output Interface - clock/Receive HDLC Controller -

Clock output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer mode or in the High-Speed

HDLC Controller Mode.

Clear-Channel Framer Mode - RxOHClk:

The XRT79L71 will output the overhead bits within the incoming DS3 or E3

frames via the RxOH output pin, upon the falling edge of this clock signal.

As a consequence, the user's local terminal equipment should use the rising

edge of this clock signal to sample the data on both the RxOH and RxOHFrame

output pins.

NOTE: This clock signal is always active.

High-Speed HDLC Controller Mode - RxHDLCClk:

This output pin functions as the Receive HDLC Controller Data bus clock out-

put. The Receive HDLC Controller block outputs the contents of all received

HDLC frames via the Receive HDLC Controller Data bus (RxHDLCDat_[7:0])

upon the rising edge of this clock signal. Hence, the user's local terminal equip-

ment should be designed/configured to sample this data upon the falling edge

of this clock signal.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 38 Page - Exar Corporation

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