XRT79L71IB datasheet(30/441 Pages) EXAR

30 / 441 page

XRT79L71

PRELIMINARY

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REV. P1.0.3

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

A10

TxCellTxed/

TxNibFrame/

ValidFCS

Transmit Cell Generator indicator/Transmit Nibble Frame Indicator/Valid

FCS Indicator output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM Mode, the Clear-Channel Framer Mode or in

the High-Speed HDLC Controller Mode.

ATM Mode - TxCellTxed:

This output pin pulses "High" each time the Transmit Cell Processor transmits a

cell to either the Transmit PLCP Processor or the Transmit DS3/E3 Framer block.

Clear-Channel Framer Mode - TxNibFrame:

This output pin pulses "High" when the last nibble of a given DS3 or E3 frame is

expected at the TxNib[3:0] input pins.

The purpose of this output pin is to alert the local terminal equipment that it

needs to begin the transmission of a new DS3 or E3 frame to the XRT79L71.

NOTE: This output pin is not active if the XRT79L71 is configured to operate in

the Serial-Mode.

High-Speed HDLC Controller Mode - ValidFCS:

The combination of the RxIdle and ValidFCS output signals are used to convey

information about data that is being output via the Receive HDLC Controller out-

put Data bus (RxHDLCDat_[7:0]).

If RxIdle = "High":

The Receive HDLC Controller block with drive this output pin "High" anytime the

flag sequence octet (0x7E) is present on the RxHDLCDat[7:0] output data bus.

If RxIdle and ValidFCS are both "High":

The Receive HDLC Controller block has received a complete HDLC frame, and

has determined that the FCS value within this HDLC frame are valid.

If RxIdle is "High" and ValidFCS is "Low":

The Receive HDLC Controller block has received a complete HDLC frame, and

has determined that the FCS value within this HDLC frame is invalid.

If RxIdle is "High" and ValidFCS is "Low":

The Receive HDLC Controller block has received an ABORT sequence.

TxPERR

Transmit Error Indicator from Link Layer:

This input signal is used to indicate that the current packet is ABORTED and

must be discarded. This input pin should only be asserted when the last byte (or

word) is be written onto the TxPData[15:0] input pins.

NOTE: This input pin is only active if the XRT79L71 has been configured to

operate in the PPP Mode.

TxPEOP

Transmit POS-PHY Interface - End of Packet:

The link layer processor toggles this output pin "High" whenever the Link Layer

Processor is writing the last byte (or word) of a given Packet into the TxP-

Data[15:0] data bus.

NOTES:

This input pin is only valid when the XRT79L71 is configured to operate

in the PPP Mode.

This input pin is only valid when the Transmit POS-PHY Interface -

Write Enable Input pin (TxPEn) is asserted.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 30 Page - Exar Corporation

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