XRT79L71IB datasheet(33/441 Pages) EXAR

33 / 441 page

áç

PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

TxTSX/

TxPSOF

Transmit - Start of Transfer/Transmit - Start of PPP Packet in Chunk Mode:

The function of this input pin depends upon whether the XRT79L71 has been

configured to operate in the Packet Mode or Cell-Chunk Mode.

Packet Mode - TxTSX:

The Link-Layer processor pulses this input pin "High" when an in-band port

address is present on the TxPData[7:0] bus.

When this input pin and TxPEN are both set "High" then the value of TxP-

Data[7:0] is the address value of the TxFIFO to be selected. Subsequent write

operations, into TxPData[15:0] will fill the TxFIFO corresponding to this inband

address.

Chunk Mode - TxPSOF:

The Link Layer processor pulses this input pin "High" in order to indicate that the

first byte (or word) of a given Packet is placed on the TxPData[15:0] pins.

NOTE: This input pin is only active if the XRT79L71 has been configured to

operate in the PPP Mode.

TxUClkO/

TxPClkO

Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Out-

put:

This output is derived from an internal PLL.

TxUClk/

TxPClk

Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Input:

The function of this input pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or in the PPP Mode.

ATM UNI Mode - TxUClk:

The Transmit UTOPIA Interface clock is used to latch the data on the Transmit

UTOPIA Data bus, into the Transmit UTOPIA Interface block. This clock signal is

also used as the timing source for circuitry used to process the ATM cell data into

and through the TxFIFO.

During Multi-PHY operation, the data on the Transmit UTOPIA Address bus pins

is sampled on the rising edge of TxUClk.

PPP Mode - TxPClk:

The Transmit POS-PHY Interface clock is used to latch the data on the Transmit

POS-PHY Data bus, into the Transmit POS-PHY Interface block. This clock sig-

nal is also used as the timing source for circuitry used to process the Packet data

into and through the TxFIFO.

TxUAddr_0

TxUAddr_1

TxUAddr_2

TxUAddr_3

TxUAddr_4

Transmit UTOPIA Address Bus:

These input pins comprise the Transmit UTOPIA Address Bus input pins. The

Transmit UTOPIA Address Bus is only in use when the XRT79L71 is operating in

the Multi-PHY mode. When the ATM Layer processor wishes to write data to a

particular UNI (PHY-Layer) device, it will provide the address of the intended UNI

on the Transmit UTOPIA Address Bus. The contents of the Transmit UTOPIA

Address Bus input pins are sampled on the rising edge of TxUClk. The UNI will

compare the data on the Transmit UTOPIA Address Bus with the pre-pro-

grammed contents of the TxUT Address Register (Address = 70h). If these two

values are identical and the TxUEN pin is asserted, then the TxUClav pin will be

driven to the appropriate state based upon the TxFIFO fill level for the Cell Level

handshake mode of operation.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 33 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 33 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL