XRT79L71IB datasheet(28/441 Pages) EXAR

28 / 441 page

XRT79L71

PRELIMINARY

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REV. P1.0.3

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

TxNib_2/

TxStuff_Ctl/

TxHDLCDat_2

Transmit Nibble Input Interface - Bit 2/Transmit PLCP Stuff Control Input/

Transmit HDLC Controller Data Bus - Bit 2 Input:

The function of this input pin depends upon whether the XRT79L71 is configured

to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller

Mode, or in the ATM/PLCP Mode.

Clear-Channel Framer Mode - TxNib_2:

If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this

input pin will function as the bit 1 input to the Transmit Nibble-Parallel input inter-

face. The Transmit Payload Data Input Interface block will sample this signal

(along with TxNib_0, TxNib_2 and TxNib_3) upon the falling edge of TxNibClk

NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the

Serial Mode.

ATM/PLCP Mode - TxStuff_Ctl:

This input pin is used to externally exercise or forego trailer nibble stuffing oppor-

tunities by the Transmit PLCP Processor. PLCP trailer nibble stuff opportunities

occur in periods of three PLCP frames (375 us). The first PLCP frame (first,

within a stuff opportunity period) will have 13 trailer nibbles appended to it. The

second PLCP frame (second within a stuff opportunity period will have 14 trailer

nibbles appended to it. The third PLCP frame (the location of the stuff opportu-

nity) will contain 13 trailer nibbles if this input pin is pulled "Low", and 14 trailer

nibbles if this input pin is pulled "High".

NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the

Direct-Mapped ATM Mode.

High-Speed HDLC Controller Mode - TxHDLCDat_2:

If the XRT79L71 is configured to operate in the High-Speed HDLC Controller

mode, then the local terminal equipment will be provided with a byte-wide Trans-

mit HDLC Controller byte-wide input interface. This input pin will function as Bit 1

within this byte wide interface.

Data, residing on the Transmit HDLC Controller byte wide input interface, will be

sampled upon the rising edge of the TxHDLCClk output signal.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 28 Page - Exar Corporation