LT3752 datasheet(33/52 Pages) AD

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LT3752/LT3752-1

Rev. C

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APPLICATIONS INFORMATION

moment the active clamp capacitor is passively switched

in to ground (due to the forward conduction of M2 body

diode) and the drain voltage increases at a slower rate

due to the loading of CCL. SWP above VIN causes IMAG

to reduce from a positive value towards zero (dVSWP/dT

= 0). As IMAG becomes negative it begins to discharge

the SWP node. Switching in M2 before IMAG reverses,

actively connects the bottom plate of CCL to ground and

allows SWP to be discharged slowly. The resulting SWP

waveform during M1 off-time appears as a square wave

with a superimposed sinusoidal peak representing ripple

voltage on CCL.

The switch M2 experiences near zero voltage switching

(ZVS) since only the body diode voltage drop appears

across it at switch turn on.

HI Side Active Clamp Topology (LT3752-1)

For high input voltage applications the VDS rating of avail-

able P-channel MOSFETs might not be high enough to

be used as the active clamp switch in the LO side active

clamp topology (Figure 13). An N-channel approach using

the HI side active clamp topology (Figure 17) should be

used. This topology requires a gate drive transformer or

a simple gate drive opto-coupler to drive the N-channel

MOSFET (M2) for switching in the active clamp capacitor

from SWP to VIN. The M1 drain voltage calculation is the

same as in the LO side active clamp case and M1 should

be rated in a similar manner. The voltage across the clamp

capacitor in the HI side architecture, however, is lower by

VIN since it is referenced to VIN.

The steady-state active clamp capacitor voltage VCCL to

reset the transformer in a HI side active clamp topology

can be approximated by:

VCCL (HI side):

(a) Steady state: VCCL = VRESET = VDS – VIN

1– D







 • VIN = VIN • VOUT •

VIN – VOUT •N

(

)

(b) Transient:

During load transients, duty cycle and hence VCCL may

increase. Replace D with DVSEC in the equation above to

calculate transient VCCL values. DVSEC guardrail can be

programmedascloseas6%higherthanDbutmayrequire

a larger margin to improve transient response. See the

previous section Programming Duty Cycle Clamp–DVSEC.

CCL should be rated for a voltage higher than the above

steady-state calculation due to tolerances in duty cycle,

load transients, voltage ripple on CCL and the effect of

voltage coefficient on capacitance value. A typical choice

for CCL is a good quality (X7R) capacitor. When using a

gate drive transformer to provide control of the active

clamp switch (M2), the external components C1, C2, R1,

D1 and T4 are required. T4 size will increase for lower

programmed switching frequencies due to a minimum

volt-secondrequirement.Alternatively,asimplegatedriver

opto-coupler can be used as a switch to control M2, for a

smallersolutionsize.Theinputsupplycapacitorforthegate

drive opto-coupler is easily charged using the housekeep-

ing supply of the LT3752-1. Common component values

are shown in the Typical Applications section.

Active Clamp Capacitor Value and Voltage Ripple

The active clamp capacitor value should be chosen based

on the amount of voltage ripple which can be tolerated

by components attached to SWP. Lower CCL values will

create larger voltage ripple (increased drain voltage for the

primary side power MOSFET) but will require less swing

in magnetizing current to move the active clamp capacitor

during duty cycle changes. Choosing too high a value for

the active clamp capacitor (beyond what is needed to keep

ripple voltage to an acceptable level) will require unneces-

sary additional flux swing during transient conditions. For

systems with flux swing detection, too high a value for the

active clamp capacitor will trigger the detection system

early and degrade transient response.

LT3752 Datasheet(PDF) 33 Page - Analog Devices

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