LT3752 datasheet(37/52 Pages) AD

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LT3752/LT3752-1

Rev. C

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APPLICATIONS INFORMATION

SS1: 2.45V to 1.25V (soft-stop fOSC, DVSEC, COMP). This

is the SS1 range for soft-stop folding back of:

(1)fOSCandDVSECfrom100%to22%(50%forLT3752-1)

of their programmed levels.

(2)COMP pin (100% to 0% of commanded peak

current).

SS1 soft-stop fOSC,DVSEC,COMPperiod (2.45Vto1.25V)

= 1.2V • CSS1/10.5µA

SS1 < 1.25V. Forward converter stops switching and SS2

pin is discharged to 0V using 2.8mA.

SS1=1.25Vto0V:WhenSS1fallsbelow0.15Vtheinternal

SS1 latch is reset. If all faults are removed, SS1 begins

charging again. If faults still remain, SS1 discharges to 0V.

SS1 soft-stop non-switching period (1.25V to 0V)

= 1.25V • CSS1/10.5µA

DVSEC rises as system input voltage falls in order to

provide a maximum duty cycle guardrail (volt-second

clamp). When system input falls below it's UVLO thresh-

old, however, this triggers a soft-stop with the converter

continuing to switch. It is important that DVSEC no longer

increases even though system input voltage may still be

falling. The LT3752/LT3752-1 achieve an upper clamp on

DVSEC by clamping the minimum level for the IVSEC pin

to 1.25V. As SS1 pin discharges during soft-stop it folds

back DVSEC. As DVSEC falls below the natural duty cycle

of the converter, the converter loop follows DVSEC. If the

system input voltage rises (IVSEC pin rises) during soft-

stop the volt-second clamp circuit further reduces DVSEC.

The I.C. chooses the lowest DVSEC commanded by either

the IVSEC pin or the SS1 soft-stop function.

Hard-Stop (SS1, SS2)

Switching immediately stops and both SS1 and SS2 pins

are rapidly discharged (Figure 18. Hard-Stop) if any of the

following faults occur (typical values):

(1) UVLO_VSEC < 0.4V: Micropower shutdown

(2) OVLO > 1.250V: System input OVLO

(3) HFB < 0.92V: Housekeeping supply UVLO

(4) OC > 96mV: Over current condition

(5) INTVCC < X(UVLO), > 16.5V (OVLO)

(6) TJ > 170°C: Thermal shutdown

(7) VIN < Y: VIN pin UVLO

(X = 4.6V, Y = 5.5V for LT3752)

(X = 6.8V, Y = 7.6V for LT3752-1)

Switching stops immediately for any of the faults listed

above. When SS1 discharges below 0.15V it begins charg-

ing again if all faults have been removed. For an over cur-

rent fault triggered by OC > 96mV, the disable of switching

will cause the OC pin voltage to fall back below 96mV.

This will allow SS1 and SS2 to recharge and eventually

attempt switching again. If the over current condition still

exists, OC pin will exceed 96mV again and the discharge/

charge cycle of SS1 and SS2 will repeat in a hiccup mode.

The non-switching dead time period during hiccup mode

reduces the average power seen by the converter in an

over current fault condition. The dead time is dominated

by SS1 recharging from 0.15V to 1.25V.

Non-switching period in over current (hiccup mode):

= 1.1V • CSS1/11.5µA

OUT, AOUT, SOUT Pulse-Skipping Mode

During load steps, initial soft-start, end of soft-stop or

light load operation (if the forward converter is designed

to operate in DCM), the loop may require pulse skipping on

the OUT pin. This occurs when the COMP pin falls below

its switching threshold. If the COMP pin falls below it's

switching threshold while OUT is turned on, the LT3752/

LT3752-1 will immediately turn OUT off ; both AOUT and

SOUTwillcompletetheirnormalsignaltimingsreferenced

from the OUT falling edge. If the COMP pin remains below

it's switching threshold at the start of the next switching

cycle, the LT3752/LT3752-1 will skip the next OUT pulse

and therefore also skip AOUT and SOUT pulses. For AOUT

control, this prevents the active clamp capacitor from be-

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