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LT3752 Datasheet(PDF) 28 Page - Analog Devices

Part # LT3752
Description  Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LT3752 Datasheet(HTML) 28 Page - Analog Devices

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LT3752/LT3752-1
28
Rev. C
For more information www.analog.com
VIN
VIN
INTVCC
VOUT
M1
RSENSE
3752 F10
RISLP
• •
LTC3752/LT3752-1
INTVCC
COMP
OUT
OC
ISENSEP
FROM
REGULATION
LOOP
ISENSEN
GND
Figure 10. Current Sensing and Programmable
Slope Compensation
APPLICATIONS INFORMATION
Adaptive leading edge blanking occurs from the start of
OUT rise and completes when OUT reaches within 1V of
its maximum level (INTVCC for LT3752, VIN for LT3752-1).
An extended blanking then occurs which is programmable
using the RTBLNK resistor given by:
tBLNK = 50ns+
2.2ns
k
•RTBLNK
,
7.32k < RTBLNK < 249k
Adaptive leading edge blanking minimizes the value re-
quiredforRTBLNK.IncreasingRTBLNKfurtherthanrequired
increases M1 minimum on time (Figure 10).
In addition, the critical volt-second clamp (DVSEC) is not
blanked. Therefore, if DVSEC decreases far enough (in soft
startfoldbackandatmaximuminputvoltage)M1mayturn
off before blanking has completed. Since OC and ISENSEP
signals are only seen when M1 is on (and after blanking
has completed), RTBLNK value should be limited by:
(2.2ns/k)RTBLNK < TVSEC(MIN) – tADAPTIVE – 50ns
where,
TVSEC(MIN) = 109(DVSEC (MAX) /(fold.fosc))
(Input(MIN)/Input(MAX))
fold = fOSC and DVSEC foldback ratio (for OUT pin)
( = 4 for LT3752 , = 2 for LT3752-1)
tADAPTIVE = OUT pin rise time to INTVCC – 1V
Example: For Figure 20 circuit, DVSEC(MAX) = 0.77,
Input(MIN)/(MAX) = 17.4V/74V, fold = 4, tADAPTIVE = 23ns
and fOSC = 240kHz,
TVSEC(MIN) = 109(0.77/(4 • 2.4 • 105)) • 17.4/74 = 188ns
(2.2ns/1k)RTBLNK < 188 – 23 – 50
RTBLNK < 52.5k (Actual Circuit Uses 34k)
Current Sensing and Programmable Slope
Compensation
The LT3752/LT3752-1 command cycle-by-cycle peak
current in the external switch and primary winding of the
forward transformer by sensing voltage across a resistor
connected in the source of the external n-channel MOSFET
(Figure 10).
The sense voltage across RSENSE is compared to a sense
threshold at the ISENSEP pin, controlled by COMP pin level.
Two sense inputs, ISENSEP and ISENSEN, are provided to
allow a Kelvin connection to RSENSE. For operation in con-
tinuous mode and above 50% duty cycle, required slope
compensation can be programmed by adding a resistor,
RISLP, in series with the ISENSEP pin. A ramped current
always flows out of the ISENSE pin. The current starts from
2µA at 0% duty cycle and linearly ramps to 33µA at 80%
duty cycle. A good starting value for RISLP is 1.5kΩ which
gives a 41mV total drop in current comparator threshold
at 65% duty cycle.
The COMP pin commands an ISENSEP threshold between
0mV and 220mV. The 220mV allows a large slope com-
pensation voltage drop to exist in RISLP without effecting
the programming of RSENSE to set maximum operational
currents in M1. An fSYNC/fOSC ratio of x (1.0 < x < 1.25)
will reduce the externally programmed slope compensa-
tion by a factor of 1.2x. If required, the external resistor
RISLP can be reprogrammed higher by a factor of 1.2x.
Overcurrent: Hiccup Mode
The LT3752/LT3752-1 use a precise 96mV sense thresh-
old at the OC pin to detect excessive peak switch current
(Figure 10). During an overload condition switching



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